Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more.
Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production environment.
Smart Stacking is particularly well-suited to advanced semiconductor applications such as Back-Side Illuminated (BSI) image sensors, RF front end modules, MEMS with cavities and emerging 3D integration.
It is a cost-effective, production-proven technology. The platform scales from 150 to 300mm wafer diameters and is compatible with various wafer types (Si, Glass, Fused silica, poly SiC,…).
The core technologies of Smart Stacking are surface conditioning, low temperature direct oxide-oxide bonding, and wafer thinning.
To address the thermal budget constraints imposed by stacking of backend of the line (BEOL) processed wafers (i.e. < 400°C), specific pre-bonding surface conditioning and post-bonding thermal treatment were developed to control and increase the bonding strength within the reduced thermal budget window (see Figure 2).
As the demand for CMOS image sensors in mobile devices continues to increase, these devices require continuous pixel shrink for higher resolution and smaller form factor. But as pixel sizes get smaller with traditional processing technologies, the fill factor gets worse and sensor efficiency degrades.
Smart Stacking for BSI image sensors involves bonding the processed wafer face down on a handle wafer, then thinning and exposing the pixel from the back of the wafer.
This provides the most direct path for light into the pixel, providing enhanced efficiency with continuous pixel shrink, minimum distortion and higher yield. Smart Stacking for BSI image sensors is compliant with military reliability standards.
With the evolution of new cellular standards and band frequencies, the demand for integrating complex RF front end modules is increasing. As the high-frequency performance of CMOS improves with process shrinks, silicon-on-engineered insulating substrates are being implemented for low-power and low-cost RF applications.
Smart Stacking is the enabling technology for silicon-on-engineered insulating substrate solutions. It combines the benefits of state of the art CMOS processes with the very low parasitic capacitance of the insulating substrate, thus providing increased speed, lower power consumption, better linearity, and more isolation than bulk silicon.
As the industry is now entering a next phase on the MEMS technology roadmap, Smart Stacking technology is very well-suited for bonding wafers with pre-etched cavities. The advantages include simplifying the process flow, allowing optimized geometries key for sensitive devices as well as permitting access to thin membranes (e.g. gyroscopes, resonators).
3D integration is becoming of critical interest for smaller, faster electronics with extended and new functionalities.
However, achieving a robust mechanical bond without introducing new materials is a requisite for maintaining manufacturing and reliability standards.
Smart Stacking based on low-temperature direct oxide-oxide bonding with sub-micron alignment is a promising path for 3D stacking of processed wafers. This integration achieves a mechanical bond between face-to-face bonded wafers or back-to-face by double transfer.
Soitec’s Smart Stacking technology is currently being leveraged in high-volume manufacturing in partnership with leading foundries and IDMs.
It provides an excellent, cost-effective solution to manufacturing challenges faced by designers as they look to new and improved technologies and integration schemes.
We have combined our core technology know-how, strong IP portfolio, industrial infrastructure, and licensing options to enable and deliver Smart Stacking as a wafer level solution serving applications on the forefront of innovation.