At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights.
The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production for high-volume manufacturing that meet all the current requirements for the 20/22nm node.
For this node, the thicknesses of the target structure are 12nm silicon and 25nm BOX to accommodate body bias strategies. The industry is referring to these wafers as UTBB, for ultra-thin body bias.
For manufacturing such wafers, the main challenges were ensuring that both the top silicon and BOX respected the extremely stringent requirements for thickness uniformity and site flatness.
The reason for this is that for undoped FD-SOI transistors, thickness uniformity is the critical element in controlling threshhold voltage (Vt) variation.
By fine tuning of elementary process steps in our Smart Cut process, we are able to produce UTBB wafers. The following illustrations highlight how we do it.
This paper is taken from the Soitec presentation given at the SOI Consortium’s FD-SOI Workshop in Taiwan (April 2011). The full presentation is freely availabe for downloading from the Consortium website.
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