5th FD-SOI Workshop (Taiwan)
Posted date : May 27, 2011

Following the April 2011 VLSI-TSA and VLSI-DAT conferences in Hsinchu, Taiwan, the SOI Consortium hosted the fifth in its series of FD-SOI Workshops.

All the presentations (as well as presentations from the previous workshops) can be downloaded from the Consortium website. Here are brief summaries.

  • Introduction (by Horacio Mendez, SOI Consortium): gives an overview of the FD-SOI advantages for mobile apps; presents the Consortium’s recent work and plans.
  • FDSOI Design Migration from Bulk at 20nm Node (ARM): recaps the results of the 20nm FD-SOI ARM Cortex M0 benchmark announced in February.
  • SRAM Analysis (by Changhwan Shin, UC Berkeley): addresses SRAM variability, concluding that for FD-SOI could get 6-sigma yield on a cell 30% smaller than bulk.
  • CMOS Technology for 20nm and Beyond (by Ali Khakifirooz, IBM): reviews approaches IBM is taking in addressing low power (LP) challenges.
  • FDSOI Substrate Readiness and Supply Chain (by Olivier Bonnin, Soitec): explains how Soitec has reached substrate readiness for ultra-thin Box and body (UTBB).
  • FDSOI – Manufacturability Perspective (by Tomasz Brozek, PDF): asks tough questions related to FD-SOI and yield, but finds no show-stoppers.
  • BSIM Models for SOI (by Sriramkumar Venugopalan, UC Berkeley): presents BSIM-IMG, “A Turnkey Compact Model for Back-gated FD-SOI MOSFETS”.
  • Si Calibrated FDSOI Modeling (by Olivier Faynot, CEA/Leti): covers their compact model for FD-SOI, which uses the surface potential approach.
  • 0.4V Technology Reliability and Applications (by Nobuyuki Sugii, LEAP): examines the relationships between speed, power, efficiency, and scaling of FD-SOI for ultra-low voltage/power (ULV/ULP).
  • Device Variability Benchmark for Bulk and FDSOI MOSFETs (by Toshiro Hiramoto, U. Tokyo): presents results from a recent MIRAI program dedicated exclusively to variability.

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