Bulk to SOI Porting Analysis
Posted date : May 27, 2011

One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology.

Objective: Analyze details of a design migration from 20LPM to 20ET

Current participants: IBM, Qualcomm (limited), Soitec, ARM, GlobalFoundries

Deliverables: Provide a comprehensive and credible answer to the question, “What will it take to port a SoC design from Bulk to FD-SOI CMOS in the most straight-forward way?” The output will be a short manual or white paper describing the design porting steps.

Key Focus areas:

  • ESD
  • Back-bias implementation, which includes substrate ties and bitcells stability
  • Analog implementation
  • Reliability, which includes soft error rate.

Timescale (tentative): Final release is currently slated to be ready in time for the DAC conference (June 5th).

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