FD-SOI: A Quick Backgrounder
Posted date : May 27, 2011

For those new to FD-SOI, here’s a short description of the basic principles.

FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and processed wafer cost over Bulk transistor.

The major obstacles in scaling both the voltage and the transistor geometry are driven by manufacturing fluctuations. Fully Depleted SOI controls transistor fluctuations by nearly eliminating the variability due to channel-dopant distribution.

The objective of  producing wafers with a thin Buried Oxide  (BOX) is to enable back-bias. The back-bias is applied through a Well contact, etched through the BOX .With back-bias, the transistor Vt can be readily controlled by appliying voltage to the  Well under the gate (fig1).

The advantage of impletmenting back-bias in FD SOI as opposed to Bulk is that the BOX acts as an isolation barrier for p-n juction leakage. The back bias can be controlled independently for the P and N transistors to optimize leakage  and performance.

Figure 1. Cross section of FD SOI transistors structure

Figure 1. Cross section of FD SOI transistors structure

Publications by Hitachi’s Yamaoka et al, show that “by using a forward back-gate bias, Ion can be increased by about + 20%. While using a reverse back-gate bias, Ioff can be reduced by about up to 90%. Even if we apply some voltages to the back gate, the substrate current does not increase”. These measurements were made at 65nm. The advantages become even more acute at 20nm and below (see Figure 2).

These transistor advantages in FD SOI, provide significant advantages for mobile SoC’s.

Target Markets Mobile computing of all kinds:  Games, smart phones, tablets, etc.
Power Provides low power at handset class performance
Performance Power/performance improves at lower voltage
Leakag Lower leakage by design
Complexity Simpler and cost-efficient manufacturing. This is particularly true when compared to 3-D transistors such as FinFETs
Design Compatibility Fully compatible with bulk, no floating body effects to worry about


For more in-depth information, see the white paper on the SOI Consortium website.

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