FD-SOI update

Data indicates that fully-depleted (FD) SOI offers an ideal combination for achieving ultra-low-power, high-performance and cost-effective manufacturability. Companies in the SOI Consortium are working together on furthering the development and technology evaluations.

February Results at the Circuit Level

A group of companies within the SOI Consortium (ARM, Global Foundries, IBM, SOITEC, ST and Leti), have collaborated to simulate the impact of using FD SOI on an ARM M0 Cortex core. These results were made available in a press release in February 2011 and are described below:

Benchmarking circuit: ARM Cortex M0 processor core

– Logic only (no memory)
– 30k Gates
– Usual Arm core used to test advanced technologies
– P&R circuit using standard EDA tools

Target techniology:

– 20nm FD-SOI

Results: Impressive advantage at low Vdd

Updated Circuit Level Results

Since the ARM M0 Cortex results released in February, the in-line Silicon has continued to improve. Based on these improvements, we have generated a revision on the Spice models and are in the process of re-simulating the M0 Cortex. We have also estimated the expected results on an ARM 9 core, as shown here:

Performance (Rev2 Model)- Comparison with the lowest leakage transistor in all cases- FD-SOI does not have an optimized Back Bias

It should be noted that these results are for the lowest leakage transistors (also the lowest performance). The “green” data point above represents a newer higher performance transistor now added to the FD SOI technology.