AMD Bulldozer Architecture Leverages 32nm SOI
Posted date : Nov 24, 2011

With performance, efficiency, and power optimization as top priorities, AMD’s innovative Bulldozer architecture is built on 32nm SOI.

As of the Fall of 2011, AMD is shipping both client and server CPUs based on the new Bulldozer architecture. The first of the new APUs (CPU + GPU) incorporating Bulldozer modules will start shipping in 2012.

All of AMD’s innovative new Bulldozer architectures are built on 32nm SOI technology fabbed by GlobalFoundries.

Bulldozer is the code name for AMD’s next-generation CPU core, which targets the two key “heavy lifting” markets:

  • servers, and
  • the high-performance end of the client platform.

As indicated on the AMD roadmap, all of the company’s CPUs for the “server” market – chips in the Opteron family – are based on the 32nm SOI Bulldozer architecture.

The roadmap for “client” products also shows key chip families for desktop processors and high-performance notebooks based on the 32nm SOI Bulldozer architecture.


OpteronInterlagos is the codename for AMD’s 12- or 16-core 32nm SOI server processors based on the new “Bulldozer” processor core. It carries the AMD Opteron™ 6200 and 6100 Series processor brands and is supported by the AMD Opteron™ 6000 Series (“Maranello”) platform.

Interlagos includes the world’s first 16-core x86 processors. The first Interlagos shipments began in August 2011 to large custom supercomputer installations: 25,000 to Oak Ridge labs and 38,000 to Los Alamos, for example.


Unlocked FX ProcessorThe latest AMD FX series marks the first retail availability of Bulldozer-based processors. Available in 8-, 6- and 4-core configurations, these CPUs targets extreme multi-display gaming, mega-tasking and HD content creation for PC and digital enthusiasts.

The new FX includes the first-ever eight-core desktop processor, which took the Guinness World Record for the “Highest Frequency of a Computer Processor,” hitting a top speed of 8.429 GHz.

Up next: APUs

AMD has dubbed the company’s new Fusion APUs the era of “Personal Supercomputing”. The A-Series APUs, codenamed Llano, that started shipping in mid-2011 are based on 32nm SOI, but their CPUs are based on the previous generation of the x86 CPU architecture, and as such are not yet Bulldozer.

However, the next generation in the A-Series APUs, codenamed Trinity and scheduled for release in 2012, will also be based on 32nm SOI with next-generation Bulldozer CPU cores.

Power-optimized design

The Bulldozer architecture is based on “modules” of two cores each. AMD explains that this means two simultaneous threads can be executed more efficiently than two threads running on a single integer core.

Bulldozer module

(Courtesy: AMD)
Bulldozer specs⁴:
> each module has 2 cores
> 213 million transistors/module
> 11 metal layers, 32nm SOI, HKMG
> 0.8 – 1.3V operation
> Area/module: 30.9mm2 (for a 2-core CPU module + 2MB L2 cache)

For each two-core module, there is a shared 2MB L2 cache. The shared L3 cache varies from 8MB to 16MB, depending on the processor.

The Bulldozer design is new from the ground-up. It required co-development of power efficiency, timing, and functionality¹. The team reduced leakage power by 95% when both cores are idle by module-level VSS (rather than VDD) power gating, first used in the 32nm Llano CPU. SOI enables this to be done without extra processing steps².

The L1 caches use an 8T storage cell. The design team said that the change from a 6T cell in 45nm to 8T in 32nm improved the low-voltage margin and read timing and reduced power³.

This game-changing architecture on SOI promises an exciting new era of high performance and low power in systems ranging from sleek but powerful notebooks to the fastest supercomputers on the planet.

1. Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU. Tim Fischer et al. IEEE ISSCC 2011, p.78.
2. An x86-64 Core Implemented in 32nm SOI CMOS, by Ravit Jotwani, et al. IEEE ISSCC 2010, p. 106.
3. Idem, Fisher et al.
4. Idem, Fisher et al.


Thank you to AMD for help on this article.

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