The latest white paper from SOI Consortium members is loaded with technical information. The full paper is available on the website. Here are some of the highlights.
In approaching a bulk-to-FD-SOI port, different perspectives can be taken:
The efforts required to port a design will depend on the exact foundry offering and associated Design Kit. Nevertheless, in essence:
FD-SOI transistors, because of their ultra-thin body, have a much closer-to-ideal behavior than classical planar bulk CMOS. For designers this translates to unique advantages at the circuit level, including:
Direct porting is an option for seeing worthwhile benefits with the fastest time-to-market. It involves swapping bulk transistors for FD-SOI transistors at constant cell layout and re-characterizing the cells.
Alternatively, if ultimate performance is sought, re-optimization of selected cells vs. exact transistor characteristics may further improve the results. The exact return on efforts would be confirmed by checking the specifications of the FD-SOI technology offered by the foundry.
With FD-SOI on ultra-thin Buried Oxide (BOx), the substrate underneath the BOx is normally tied to Vdd or Gnd. This is not disruptive for the design and is handled by substrate ties exactly in the same way as well biasing in classical bulk CMOS technology; only now the contact to the substrate is made through the BOx.
Then there is the option to have “active” back-bias, to shift the VT or, equivalently, the Ion/Ioff operating point – by shifting the voltage applied under the BOx. In particular, dynamic back-biasing is an extremely efficient technique to either boost performance or cut leakage according to the workload. It is more efficient and usable than the similar body-bias technique on bulk, due to a very good body factor plus the ability to push significantly further the bias voltage without unacceptable leakage. The bias voltage is applied under the BOx using the same substrate tie cells as above, placed in the chip layout every so many microns (PDK-dependent), like bulk substrate ties.
For easy porting, the bitcells provided in the FD-SOI PDK should have the same abstract (footprint) as those provided with the bulk CMOS PDK.
Then existing compilers can be re-used, with updated characterization (timing, power, etc.). For the periphery, options are the same as for standard cells: direct port for fastest time-to-market or re-optimization for ultimate performance.
Integration of thick gate-oxide transistors on FD-SOI is not an issue. Non-FET devices will have a counterpart in the FD-SOI device menu. Some of them may actually be provided as Bulk devices, through Bulk-FD-SOI co-integration (by locally etching off the top silicon and BOx to give access to the underlying Bulk substrate). In some cases and depending on foundry choices, there might be a few devices used in the original Bulk design that have no direct counterpart in the FD-SOI-compatible device menu: then it would be necessary to adapt the IP design to come up with a solution based on replacement devices.
SOC porting strategy and design flow