FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open
Posted date : Feb 7, 2012

Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)

The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.

It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.

The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.

Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.

The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)

This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.

Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.

The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.

Here’s a preview of program – you won’t want to miss it.

7:30am	Badge pick up & On-site registration
8:00am	Breakfast
8:30am	Introduction by Carlos Mazure (Soitec)
8:40am	Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Design by Philippe Flatresse (ST Microelectronics)
9:10am	Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Technology by Michel Haond (ST Microelectronics)
9:40am	Recent Advances in FDSOI by Bruce Doris (IBM)
10:10am	Coffee Break
10:30am	Library and Physical IP Porting for FDSOI by Jean-Luc Pelloie (ARM)
11:00am	20nm FDSOI Models by Brian Chen (Accelicon & SOI Consortium)
11:30am	FinFET on SOI by Terrence Hook (IBM)
12:00pm	Lunch
1:00pm	Enabling Substrate Technology for a Large Volume Fully Depleted Standard by Christophe Maleville (Soitec)
1:30pm	Strain Options for FDSOI by Olivier Faynot (CEA – Leti)
2:00pm	Advanced FDSOI Design by Bora Nikolic (UC Berkeley)
2:20pm	Closing Remarks by Horacio Mendez (SOI Consortium)
2:30pm	Networking and coffee buffet