The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.
Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technology, and can be on SOI or bulk) and other Multi-gate (MuGFET) devices each having compelling advantages in their favor.
Designers are considering the power and performance needs of their applications, assessing the manufacturing risks and evaluating the importance of extending current IP – which makes FD-SOI a very strong contender for current and upcoming nodes.
The recent SOI Industry Consortium announcement indicated that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
The Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of representative IP blocks, such as ARM cores and memory controllers. Here are some of the potential implications of what they’re saying.
• Peak performance is comparable with the much leakier ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve.
FD-SOI peak performance is comparable to that of GP, and significantly better than LP (low power) technologies.
The dynamic power gap, however, gets better and better as you can reduce the power supply voltage (i.e. when you’re not shooting for extreme operating frequency) — because the drop in performance when the supply voltage Vdd is lowered is much less marked with a fully-depleted technology.
The trick is, 1) not all portions of an SOC need highest possible performance and 2) even those that do need that performance only a fraction of the time — when running very demanding scenarios. So when you consider the dynamic power at chip level across use cases, then your overall dynamic power is dramatically better.
This also means, if you have a chip in bulk technology (LP or G) that runs fine in terms of performance but you’d like to cut its total power, then planar FD-SOI is a great solution.
• The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).
One of the great problems of traditional bulk CMOS is that SRAM memories quickly become unstable if their Vdd is reduced. Being unable to reduce Vdd, you cannot lower their power consumption even when you don’t need maximum access speed from them. By contrast, fully-depleted technologies enable you to operate both logic and SRAM at reduced Vdd.
• The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency.
• Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6V, critical paths on 28nm FD-SOI circuits were more than 50 percent faster than the General Purpose technology and more than twice as fast as Low Power technology;
With respect to dynamic power consumption (the power lost in switching), it’s proportional to the square of Vdd. So if you reduce Vdd and still hit the target frequency, you get a bigsavings in dynamic power consumption.
Leakage power – AKA static power – is the power lost when sub-threshold currents wander away even when the transistor is off. It’s the major cause of wasted power in standby mode. The Consortium study found that FD-SOI does better than both G and LP bulk technologies at 28nm in terms of leaky transistors.
STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.
Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog. Look for Part 3 of this blog series on the SOI Consortium study the week of 27 February 2012.
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