At the SOI Consortium’s 6th FD-SOI workshop (held just after ISSCC), excellent talks were given by STMicroelectronics, IBM, ARM, Leti, Soitec, Accelicon and UC Berkeley. Most of the presentations are freely available for downloading from the SOI Consortium website.
As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD-SOI is a significant driving force.”
Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond [STMicroelectronics, Soitec] This document considers the challenges to obtain competitive silicon technology for the upcoming generation of System-On-Chip ICs. The full document can be freely downloaded from the Consortium website. Also, please see pages 1-3 of this edition of ASN for highlights and excerpts.
20nm FD-SOI logic evaluation model cards are now available through the SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required. Please contact Horacio Mendez, Executive Director of the SOI Consortium at email@example.com to get a copy.
You must be logged in to post a comment.