Horacio Mendez, executive director of the SOI Industry Consortium noted that FD-SOI also represents a low risk in terms of manufacturing for upcoming nodes.
“FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” he said. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”
For many if not most designers, extending the life of existing planar bulk CMOS designs will make good sense. With a planar FD-SOI solution, these existing designs and related IP can be migrated in a comparatively straightforward way, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology with minimal risk and lower cost.
The SOI Consortium study also points out that FD-SOI is compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks (not available with FinFET designs), such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.
Fully depleted transistor architectures such as Planar FD-SOI, FinFET (which is also a fully-depleted technology, and can be on SOI or bulk) and other Multi-gate (MuGFET) devices each having compelling advantages in their favor.
Designers are considering the power and performance needs of their applications, assessing the manufacturing risks and evaluating the importance of extending current IP – which makes FD-SOI a very strong contender for current and upcoming nodes.
The Consortium study indicated that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
The Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of representative IP blocks, such as ARM cores and memory controllers. Here are some of the potential implications of what they’re saying.
• Peak performance is comparable with the much leakier ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve.
FD-SOI peak performance is comparable to that of GP, and significantly better than LP (low power) technologies.
The dynamic power gap, however, gets better and better as you can reduce the power supply voltage (i.e. when you’re not shooting for extreme operating frequency) — because the drop in performance when the supply voltage (Vdd) is lowered is much less marked with a fully-depleted technology.
The trick is, 1) not all portions of an SOC need highest possible performance and 2) even those that do need that performance only need it a fraction of the time — when running very demanding scenarios. So when you consider the dynamic power at chip level across use cases, then your overall dynamic power is dramatically better.
This also means, if you have a chip in bulk technology (LP or G) that runs fine in terms of performance but you’d like to cut its total power, then planar FD-SOI is a great solution.
• The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).
One of the great problems of traditional bulk CMOS is that SRAM memories quickly become unstable if their Vdd is reduced. Being unable to reduce Vdd, you cannot lower their power consumption even when you don’t need maximum access speed from them. By contrast, fully-depleted technologies enable you to operate both logic and SRAM at reduced Vdd.
• The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency.
• Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6V, critical paths on 28nm FD-SOI circuits were more than 50 percent faster than the General Purpose technology and more than twice as fast as Low Power technology.
With respect to dynamic power consumption (the power lost in switching), it’s proportional to the square of Vdd. So if you reduce Vdd and still hit the target frequency, you get a bigsavings in dynamic power consumption.
Leakage power – AKA static power – is the power lost when sub-threshold currents wander away even when the transistor is off. It’s the major cause of wasted power in standby mode. The Consortium study found that FD-SOI does better than both G and LP bulk technologies at 28nm in terms of leaky transistors.
The study provided silicon proof that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
Armed with the information from the 28nm bulk vs. FD-SOI benchmarking study, the SOI Consortium members then did new benchmark simulations at the 20nm node. This confirmed the trends they saw in silicon at 28nm. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):
Here’s the graphic that says it all. Follow the suggestions in the annotations to see how the power vs. performance trade-off works.
To use this graph: pick any point on the lower, bulk line, then move horizontally to the left to see how much less power it will take to hit the same frequency with FD-SOI. By adjusting Back Bias, FD can be changed from: High Performance Mode TO Leakage Saving Mode.
Comparing SOC power and performance for planar FD-SOI vs. standard (planar) bulk silicon design at the 20nm node.
(a) Reverse back-bias allows you to cut leakage, here by a factor of 10
(b) This line is 20 nm FD-SOI with back biasing
(c) Or with back-biasing FD-SOI, you can hit over 269 MHZ using 120 mW at 1 V power supply
(1) This line is 20 nm Bulk
(2) This line is 20 nm FD-SOI
(3) Bulk takes over 130 mW to hit frequency of about 223 MHz with supply voltage of 1 V
(4) To hit the same with FD-SOI takes just over 100 mW and a supply voltage of just 0.9 V
(Courtesy: SOI Consortium)
Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this article.