The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn. In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group.
As you no doubt know by now, at CES a few weeks ago, ST-Ericsson showed the new NovaThor L8580, which integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die. Process technology and manufacturing credit goes to ST. In a live video from the show, the chip reached 2.8GHz in a high-performance demo, and in a low-power demo hit 1GHz using just 0.636V (which would take 1.1V on bulk).
Since then, Giorgio Cesana, Director of Technology Marketing at STMicroelectronics, has been everywhere, responding to questions from readers and correcting misunderstandings as they arise.
One of the top things people want to know more about is biasing in FD-SOI, which can provide a big performance boost or huge power savings.
In case you missed it, here’s what Giorgio had to say to questions posed in the big LinkedIn Semiconductor Professional’s Group:
Thank you all for this interesting discussion and for giving me the opportunity to provide more details about the ST 28nm FD-SOI technology. I hope this clarifies any misunderstandings.”
Body bias, or more properly back bias (because biasing is done on the back face of the transistor) is a way to electrically control the Vt of the device by controlling of the polarization of the wells.
Conceptually, it is like having the planar transistor controlled by two gates: the real “classical” gate, we build with a HKMG, gate-first manufacturing approach, and a virtual gate (represented in the video with a transparent gate below the transistor) that represents the capability to control the transistor through biasing.
The back gate is the “virtual” one. It does not require any extra manufacturing steps to be fabricated. It is created simply by polarizing the well.
The particular FD-SOI technology that ST is using, called UTTB (Ultra Thin Body and Box), benefits from a extremely thin (25nm) Buried Oxide (BOX) which enables extremely efficient control of the transistor threshold voltage through the biasing, up to 80mV/V. In addition, because of the insulator in FD-SOI, biasing is not limited to 300mV like in bulk technologies, allowing an extremely wide dynamic control of the transistor Vt.
In terms of biasing efficiency, this past Dec 10th we published some figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at 0.6V. That said, exploiting body biasing is a matter of making a design that provides an independent supply to the wells, managed through the power supply controller, to optimize the Vt to reach proper energy efficiency, balancing the static and dynamic part of the power consumption. Of course biasing conditions should be considered at design optimization and sign-off phase.
Finally body/back biasing in FinFETs simply does not work, because the transistor channel is vertical and the gate controls 3 sides of the channel. The 4th side (the one sitting on the substrate) is too narrow to be influenced through body biasing. Body biasing is simply not an option with FinFETs.
Someone at one of the big programmable device companies then asked a follow-up question on the implementation. Giorgio responded:
In 28nm FD-SOI, threshold-voltage centering is a function of the gate work function, where the Vt is controlled by implanting a ground plane (GP) below the BOX (Buried Oxide). Depending on its type (N or P), Vt can be raised by more than 50mV, allowing the manufacturer to offer two device flavors: regular Vt and low Vt.
Threshold voltage is also statically controlled by modulating the gate length. ST’s multi-channel standard-cell library allows us to modulate the gate length up to +16nm, offering a static leakage control of up to 50x for a single Vt design, almost twice the leakage control offered by dual-Vt designs plus multi-channel libraries of competing bulk planar technologies.
Body bias is just one way to modulate the threshold voltage, and the dynamic nature of the control allows new and innovative design solutions to be implemented for extremely energy efficient designs.
I should note that body-bias usage is not mandatory in FD-SOI: we can make devices without using it and which still benefit from a good speed/power balance, low Vmin memories, better device variability, and all the other benefits FD-SOI processing offer. Chip architects can also decide to limit body-bias adoption only to some critical blocks/IPs in the SoC for the best trade-off between optimal energy efficiency and implementation simplicity. For further reference, you may read F. Arnaud, “Switching Energy Efficiency Optimization for Advanced CPU thanks to UTBB Technology,” IEDM 2012.
FD-SOI vs. PD-SOI: Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect.
In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.
Self-heating: Self-heating is also a problem that exists with Partially-Depleted SOI technologies, where the Buried Oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects.
UTBB FD-SOI technology offers two advantages to overcome this self-heating:
– The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;
– The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.
Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.
We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.
Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.
Manufacturability: to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.
Additional recommended reading:
– O. Faynot et al, “Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond”, International Electron Device Meeting Technical Digest, 2010
– Advantages of UTBB FD-SOI: A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012*, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES.
*Editor’s note: ETSOI is what IBM calls its flavor of FD-SOI.
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