IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers
Posted date : May 17, 2013

IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
Hyatt Regency Monterey Hotel and Spa, Monterey, California
October 7th thru 10th, 2013

In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS technology: The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. An additional third track on 3D Integration is also being included, which will emphasize invited talks from world-renowned experts in 3D technology as well as contributed talks from leading research groups and industry.

So all-in-all, attendees can access essentially three conferences with one registration fee, covering three topics at the heart of today’s industry plans:

• Silicon on Insulator (SOI) – Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-on-Insulator technology, including CMOS, photonics, sensors, NEMS and more. The conference will cover topics spanning from material engineering to circuits and applications, through devices and modeling. There is no better place than this conference to understand the underlying physics of FinFET as fully-depleted devices have always been an important topic.
• 3D Integration – 3D Integration allows us to scale integrated circuits “orthogonally” in addition to classical 2D device and interconnect scaling. A dedicated session will address the unique features of such stacking with special emphasis on wafer-level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques and bonding methods, as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed.
• Subthreshold Microelectronics – Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low-power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics.

Conference format

This year, the conference will run two parallel sessions for SOI and Subthreshold Microelectronics. A joint technical session dedicated to 3D integration will also be hosted in addition to the parallel sessions.

The rump session will lead to lively discussions about the next big changes that will occur in CMOS devices.

Of course, the social events will be maintained as usual. The welcome reception, banquet dinner and cookout are excellent opportunities for people from different backgrounds to meet in a friendly atmosphere, especially this year. There will be specialists from the different fields described above, representatives from established industries as well as startups, professors and scientists from universities and research institutes all over the world. This will be a perfect mix to generate new ideas, start collaborations and initiate new projects.

Optional classes

On top of the regular sessions, this year the conference will offer attendees the possibility to follow one of two different short courses as well as one of two different fundamentals classes.

One short course will focus on 14nm Node Design Methodology (both bulk and SOI, FinFET and planar) and the 3D short course will cover the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects in 3D silicon and packaging.

The SOI fundamentals class will discuss the post-silicon era, including device and material aspects.

The Sub-Vt fundamentals class will cover design techniques for robust sub-Vt operation of integrated circuits. Two key areas will be covered by experts in their fields. First, Professor Massimo Alioto (U. di Sienna, Intel Labs) will instruct attendees on sub-threshold VLSI digital circuits and systems, from microprocessors to memories. Second, Professor Peter Kinget (Columbia U.) will review the challenges for ultra-low-voltage analog and RF circuits and discuss design opportunities to circumvent them. This class is fundamental for anyone considering low-voltage and sub-Vt operation in circuit design.

Location

This year, the conference will take place in the splendid Hyatt Regency Monterey Hotel and Spa, located in Monterey, CA, a beautiful waterfront community on the central coast of California.

This area offers breathtaking scenery and a profusion of indoor and outdoor activities.

Important dates

Paper submission deadline: 31 May, 2013
Notification of acceptance: 30 June, 2013
Short course date: 7 October, 2013
Conference date: 7 – 10 October, 2013

More details are available on the S3S website.