At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor.
Here are some of the highlights (the complete presentations are all available from the CMP website).
FD-SOI: From Successful Collaborative R&D to Successful Silicon Results
Presented by Philippe Magarshack, Technology R&D Group Vice-President and Central CAD GM at STMicroelectronics – Download pdf
- In this general overview of their ultra-thin body & BoX approach (UTBB), he said that the process technology is very simple, with 12-15% fewer steps
- Starting at 28nm, they see at least 3 generations
- They’ve finalized things with GlobalFoundries
- It’s particularly good for low-power and analog designers
- For analog, it’s a whole new playing field, with “wonderful properties” for circuit design techniques (6x better gain, no pocket implants…)
Design Infrastructure to Support Advanced FD-SOI Below 20nm
Presented by Jean-Marc Talbot, Senior Director of Engineering Analog & Mixed Signal at Mentor Graphics Grenoble R&D Center – Download pdf
- Mentor did some awesome work on ST’s FD-SOI project. The challenge was moving from the models (which were done by Leti) to robust circuit simulators in under two years – which they did.
- ST had existing characterization tools that Mentor integrated tightly for FD-SOI and did specific tuning for the SPICE engine, resulting in a 5x speed-up in characterization!
- “The design infrastructure to support FD-SOI technology is up and running,” he concluded.
Roadmap Towards 10nm FD-SOI Node
Presented by Laurent Malier, CEO of CEA-Leti – Download pdf
- Leti has silicon layers down to 3.5nm
- For boosting pFETs with SiGe, they’re seeing better results with FDSOI than bulk FinFETs.
The advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
- The path to 10nm FD-SOI is already defined. “We are really confident in the roadmap,” he said.
- At 10nm all the benefits remain. Models for 10nm will be available Q1 ’14, and the design kits in Q3 ’14.
- Leti is working with Mentor, with ST in Crolles (near Grenoble) and with IBM in NY on optimization.
A few other notables from the DATE conference:
- In a “Testimonial” session, ST Advanced I/O design engineer Hubert Degoirat talked about designing high-speed I/O Interfaces in 28nm FDSOI. They used MunEDA’s WiCkeD analysis and optimization tools (which he said were very user-friendly). This let them do things like reduce the propagation delay of a voltage comparator by about 35%.
- At the CMP booth, Technical Director Kholdoun Torki said that requests for the 28nm FD-SOI PDK are coming in fast and furious. As you may recall reading in a previous blog, CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same ARM-core based technology that GF will be rolling out in high-volume. As of today, CMP’s gotten requests from over 50 institutions across the globe.