Fully-Depleted SOI Workshop Follows VLSI in Kyoto
Posted date : Jun 6, 2013

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto.

The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).

Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.


These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.

The 28nm FD-SOI technology offer:

  • 28nm FD-SOI Industrial Solution: Overview of Silicon-Proven Key Benefits – Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
  • SoC Differentiation using FD-SOI – A Manufacturing Partner’s Perspective – Shigeru Shimauchi, Japan General Manager, GlobalFoundries
  • Ultra Thin Body and Buried Oxide Substrate Supply Chain – Nobuhiko Noto, Deputy General Manager – Advanced Wafers Dept. – Technology & Development, SEH

Design methodologies:

  • Architectural Choices and Design Implementation Methodologies for Exploiting Extended FD-SOI DVFS and Body Bias Capabilities (short course) – David Jacquet, Sr. Principal Engineer, Design & Architecture for Energy Efficiency CPU & GPU Subsystem, STMicroelectronics
  • SoC Design for FD-SOI – Dr. Wayne Dai, CEO, VeriSilicon

Advances in Technology Development:

  • Advances and Silicon Results on 14nm planar FD-SOI Technology – Carlo Reita, CMOS Components Program Manager, CEA-Leti
  • Elements for the Next Generation FinFET CMOS Technology – Terence Hook, Sr. Technical Staff Member, IBM Semiconductor R&D Center (he also wrote an extremely popular ASN article on FinFETs on SOI recently – click here if you missed it)

The organizers for this event are:

  • Horacio Mendez
Executive Director, SOI Industry Consortium
  • Philippe Magarshack
Executive VP, Design Enablement and Services, Digital Sector, STMicroelectronics
  • Joel Hartmann
Executive VP, FE Manufacturing and Process R&D, Digital Sector, STMicroelectronics
  • Mike Noonen
Executive VP, Global Sales, Marketing, Design & Quality, GlobalFoundries

BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.

Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).

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