FD-SOI with back-biasing* (BB – also referred to as body-biasing) is an immensely powerful tool, especially for getting great performance at very low voltages with extremely low leakage.
Implemented on a smartphone processor, it’s what would give you that extra day of battery life or get you to 3GHz. But what does it mean for the SOC designer?
Back-biasing has been the subject of a lively discussion on the new LinkedIn FDSOI Design Community group. There are some very heavy hitters here from a wide range of companies – if you’re looking for expert advice, it’s an excellent place to go. Of course, people there are speaking for themselves, not necessarily for their companies. Here are brief summaries and excerpts of some of the comments.
Back biasing, they agree, can be fairly basic (e.g., with a common bias for the whole chip) or more sophisticated (with, for example, a separate bias for each block). Its implementation requires efforts comparable to other design techniques commonly used in modern low-power chips; however, with FD-SOI, its efficiency is really impressive – perhaps giving you as much as the equivalent of about a process node’s worth of improvement. At the system level, (dynamic) back-biasing is very similar to what designers have been doing for years in planar bulk low-power designs with “dynamic voltage and frequency scaling” (aka DVFS), so using back-bias as a power management technique is not overly complex if you’ve already implemented DVFS – which, by the way, is suffering from diminishing returns in bulk at the latest nodes.
One of the group’s experts notes that, “…adaptive back-biasing and Vdd control (per-chip based on speed, but not time-varying) is not significantly more complex than just per-chip Vdd control—actually, could be easier if it reduces Vdd range—but is more effective at reducing power, especially at high temperature and with process variation taken into account.”
Incidentally, you get can ST’s 28nm FD-SOI PDK from CMP (click here for details—CMP’s already had over 110 requests for it). With this platform, designers benefit from the fact that back-bias support is “built-in” – but how they exploit it in their design is still their choice, of course.
Whether you use ST’s PDK or go it alone, as one participant notes, “…using back biasing to reduce the effect of process and temperature variation can make the designers life much easier by greatly reducing the spread of performance that they have to close timing over. It also reduces power consumption by allowing operation at consistently lower (and more constant) supply voltages, which in turn eases the electromigration and power density problems which are becoming increasingly severe in each new node and are taking more and more time and effort to fix.”
So in the end, these folks agree, back-biasing in FD-SOI applies to all applications and makes design easier, not harder.
*What is back-biasing (BB)?
As explained last year in a white paper by ST & Soitec, in FD-SOI:
Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage (Vt), to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.
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