Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. hosted an “SOI Technology Summit” in Shanghai, China.
Executives of leading companies, universities and institutes, covering all the segments (substrate, design, manufacturing, EDA, IP, etc.) gathered to discuss the solutions to scaling challenges and the market opportunities for FD-SOI in China.
Handel Jones from IBS presented the IC market overview (available here) and detailed the cost difference between the different available technologies. He made the point that FD-SOI is cost competitive at 28nm and has the advantage at 20nm.
David Jacquet from ST highlighted (available here) the design benefits of back-biasing (the FD-SOI version of body biasing), which is only going to be available in FD-SOI technology since it cannot be implemented in planar bulk or FinFET in an effective manner. ST showed how back bias can provide real time optimization of the power-performance trade off and therefore give the most efficient mobile power saving results.
XMC’s Simon Yang gave a foundry manufacturing perspective on FD-SOI technology (available here), confirming that FD-SOI has a lot of advantages. In particular, it is perceived as the simplest way to enter the realm of fully depleted technologies. Also, he emphasized the necessity that the cost of FD-SOI be lower than competitive technologies, which aligned well with Handel Jones’ cost analysis. The wafer manufacturers also confirmed that the substrate price will enable the technology to be lowest cost.
Zhongli Liu, a very highly respected professor at IM CAS urged the Chinese IC industry to see the golden opportunity in FD-SOI technology. He detailed the technology benefits with well-chosen case studies (available here) and concluded that FD-SOI has broader markets since it has perfect features to match the needs of the mobile applications.
Rama Divakaruni from IBM presented a compelling talk on the IBM scaling path at 14nm, 10nm and 7nm (available here). For calculation-intensive applications such as servers, IBM is developing a 14nm FinFET on SOI with eDRAM that provide significant value propositions. Rama reminded the audience that IBM has developed both FD-SOI and FinFET on SOI, the latter being more adapted for IBM’s applications. However, depending on application and design style FD-SOI might be better suited.
SEH, SunEdison and Soitec presented wafer specifications and available capacity for RF-SOI, FD-SOI and FinFET on SOI. They showcased RF-SOI to demonstrate that SOI can be a mainstream solution meeting the cost and volume of the market demand.
Panel discussions at the end of the workshop were passionate regarding China’s opportunity to develop FD-SOI capacity, which could be a great accelerating factor for the China IC industry. This would require a commitment from foundries and design companies, which all agreed looks like the right thing to do.
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