Design & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.
After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm). He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.
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