CEA-Leti announced that Leti-UTSOI2, the first complete compact model that enlarges the physically described bias range for designers, is available in all major SPICE simulators (press release here). Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. ST and Leti researchers presented UTSOI2 at IEDM 13. The model is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.
“Enlarging the back biasing range accessible to the design community is key to optimizing the trade-off between performance and power consumption for UTBB technology,” said Thierry Poiroux, research engineer at Leti and model co-developer. “This provides more opportunities to utilize FDSOI’s advantages for mobile devices and other applications that require efficient energy use.”
The model’s development was supported by STMicroelectronics and partly funded by the ENIAC JU Places2Be project.
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