2014’s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise.
But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year. In fact, there was so much happening that we’ll review 2013 in two posts – this post is about FD-SOI; in the next post we’ll cover RF-SOI and FinFETs.
Highs, lows, and the promise of an extra day
It was just a year ago that you read in the first ASN post of 2013 about ST-Ericsson’s NovaThor™ L8580 ModAp: at 2.5GHz it was “the world’s fastest and lowest-power integrated LTE smartphone platform” at CES ’13 in Las Vegas. Then in February in Barcelona ST announced that its 28nm FD-SOI technology clocked in at 3GHz, but what was really amazing was that it got 1GHz using using just 0.6V VDD, aka the “supply voltage”, which is the main voltage “in” that powers the chip. No one had been able to run stably on that low a voltage before. 28nm FD-SOI got you a full extra day before you had to recharge your device.
But then of course came the sad news that the plug was pulled on ST-E. Happily the technology moved into the ST fold, and the 28nm process is now ramping in volume, with 14nm is set to debut shortly.
May was a big month. ST’s FD-SOI got the EETimes ACE Award for Energy Technology – and the company announced it had started winning FD-SOI customers. We also got the news of a big public-private funding boost, to the tune of €360M, for the Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe). It is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL. A 3-year public-private project involving 500 engineers from 19 members in seven countries, it’s looking to enable volume manufacturing in Europe from 28nm down to 10nm.
Also in May, Leti told us that they’d gotten silicon layers down to 3.5nm, and for boosting pFETs with SiGe, were seeing better results with FD-SOI than bulk FinFETs. What’s more, they found that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
In August, the French government upped the ante with a 600 million Euro investment in the Nano2017 program, which was in addition to the 3.5 billion Euros that ST and partners had already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).
In October, Leti said it would have the 10nm FD-SOI PDK ready in June of 2014.
In November, the wafer supply chain got a boost when SOI wafer suppliers Soitec and SunEdison (formerly MEMC) ended their longstanding legal feud and entered into a patent cross-license agreement.
At IEDM in December Leti announced UTSOI2, a compact model for electrical simulations. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers use before they run silicon. Dedicated to Ultra-Thin Body and Box (UTBB) FD-SOI technology, UTSOI2 accurately describes independent double gate operation for sub-20nm nodes. Also at IEDM, ST, Leti, IBM, Renesas, Soitec and GlobalFoundries presented the big paper showing great results for 14nm FD-SOI.
So 2014 promises to be an excellent year. Stayed tuned – next up we’ll review the great strides made in RF-SOI and SOI-FinFETs.
From all of us here at ASN, wishing you a safe, happy, healthy, prosperous and innovative New Year!
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