ST Article in EETimes Details How FD-SOI Supports Moore’s Law
Posted date : Mar 19, 2014



A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it).  Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm.

Remont explains how structurally it is the most cost-effective sub-30nm process technology because FD-SOI is much simpler. In an interesting twist, he goes on to describe how forward body biasing (FBB) allows for dynamic power / leakage / frequency tuning linked to datacenter load. “With this, energy use would be proportional to workload and FD-SOI could reduce global data center power by up to 50 per cent,” he says.

In terms of performance, he says, “…the switch from 28nm Bulk CMOS to 28nm FD-SOI can improve circuit speed by as much as 35%. Even with this performance, FD-SOI transistors run cooler, because of lower leakage, wider voltage scaling and FBB all leading to higher power efficiency.

He concludes that FD-SOI will enable the industry to validate Moore’s Law down to 10nm. A highly recommended read.

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