To date, over 40 readers have commented on Handel Jones’ (IBS) EETimes post entitled FinFETs Not the Best Silicon Road (read post here). He noted that, “…next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today’s 28nm bulk HKMG CMOS…”. He then went on to say, “One option […] is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.”
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