Cadence has announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. (See Cadence press release here.) On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, which the company says is an ideal solution for inter-chip USB applications. Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process
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