Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher.
But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.
In mid-June, Samsung posted a video of their DAC presentation, Samsung 28nm technology for the next big thing on YouTube. Presented by JW Hwang, Principal Engineer for Samsung Electronics, it runs almost 14 minutes long, with the entire second half devoted to 28nm FD-SOI. Here are some key points made therein:
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Samsung DAC ’14 video – process complexity vs. performance/power. |
Samsung DAC ’14 video – 28nm FD-SOI is product-proven |
Here at ASN, of course, there was the terrific piece by industry expert Handel Jones (IBS) entitled FD-SOI: The Best Enabler for Mobile Growth and Innovation. IBS concludes the benefits of FD-SOI are overwhelming for mobile through Q4/2017. Jones also looks for it to have a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs.
Also in ASN, we covered the SOI Papers at the 2014 VLSI Symposia. Three top SOI-based papers included one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs, and the two on 10nm SOI FinFETS. (In Part 2, we covered the rest of the SOI papers.)
Elsewhere, we saw high-profile, open debate, which is excellent and necessary. Semiwiki has been a great platform for discussion, with a steady flow of FD-SOI articles – many of which generate ferociously active discussions in the comments section. Here’s a round-up of what went on this summer:
Next, check out this interesting post in SemiconductorEngineering by Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. She gives a very informative perspective on “Power Reduction Techniques” (7 Aug. ’14) in bulk planar, FD-SOI and FinFETs. She talks about how biasing in FD-SOI is highly effective, then goes on to summarize various power-reduction techniques by process node. There’s an excellent summary in her graphic (her Figure 2):
There’s also a terrific chart in the same article based on the annual Synopsys’ Global User Survey (GUS), indicating which power techniques are used most in which applications (mobile, automotive, networking, etc.).
If talk on LinkedIn is any indication, the design community in India is very interested in FD-SOI. EE Herald published a much-shared interview with ST’s CAD/design solutions director in India (18 July ’14), entitled FDSOI; The only semiconductor tech to continue Moore’s Law down to 10nm. It gives an excellent overview of the technology, answering some of the basic questions designers are asking.
Finally, the folks at the silicon prototyping brokerage CMP pointed us at a bit of humor – and as they say, a picture’s worth a thousand words….
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