Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher.
But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.
In mid-June, Samsung posted a video of their DAC presentation, Samsung 28nm technology for the next big thing on YouTube. Presented by JW Hwang, Principal Engineer for Samsung Electronics, it runs almost 14 minutes long, with the entire second half devoted to 28nm FD-SOI. Here are some key points made therein:
- The smartphone market is saturating, except in China.
- Internet of Things (IoT) is The Next Big Thing – and it’s a far bigger market (heading towards $9 trillion per IDC) than smartphones. It’s about affordability & connectivity, with a lot of sensors and generating a lot of data (which will need low-power processing).
- 28nm is the sweet spot, and FD-SOI simplifies processing, lowering costs – and it gets better performance.
- Designers shouldn’t be afraid of FD-SOI, as the design flow is the same as bulk planar, and there’s a lot to be gained by body biasing.
- Most of the IP is already product-proven, and the PDK is currently available.
- The technology transfer from ST to Samsung is underway, and Samsung expects to have it fully qualified for high volume by March 2015.
- A second generation with additional IP that will further decrease chip size is also in the works.
Samsung DAC ’14 video – process complexity vs. performance/power.
Samsung DAC ’14 video – 28nm FD-SOI is product-proven
Here at ASN, of course, there was the terrific piece by industry expert Handel Jones (IBS) entitled FD-SOI: The Best Enabler for Mobile Growth and Innovation. IBS concludes the benefits of FD-SOI are overwhelming for mobile through Q4/2017. Jones also looks for it to have a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs.
Also in ASN, we covered the SOI Papers at the 2014 VLSI Symposia. Three top SOI-based papers included one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs, and the two on 10nm SOI FinFETS. (In Part 2, we covered the rest of the SOI papers.)
Elsewhere, we saw high-profile, open debate, which is excellent and necessary. Semiwiki has been a great platform for discussion, with a steady flow of FD-SOI articles – many of which generate ferociously active discussions in the comments section. Here’s a round-up of what went on this summer:
- Is SOI Really Less Expensive? by Scotten Jones (24 June ’14) generated a whopping 56 comments. Jones’ company, IC Knowledge, used its IC cost modeling on bulk planar, FD-SOI, bulk FinFETs and SOI FinFETs. Jones concluded that at 14nm, costs were fairly comparable, which was hotly debated by readers (with FD-SOI supporters fortifying their claim that it comes in significantly cheaper). However, no one quibbled with Jones’ final conclusion: “Decisions on which process to pursue are therefore expected to be driven by factors other than cost.”
- Keywords: FD-SOI, Cost, FinFET by Eric Esteve (15 July ’14) followed up on Jones’ piece, generating another super-heated round of comments: 41 in all. Esteve dove into the different approaches to multiple threshold voltages (Vt) between FD-SOI and FinFET, and looked at the advantages of biasing in FD-SOI, concluding that FD-SOI should do 10% better on cost than Jones projected. Heavy hitters from all sides chimed in, many with very insightful and sometimes deeply technical information and explanations.
- Setting the Record Straight on FD-SOI Costs by Scotten Jones (21 July 14) pushed back on the Esteve “keyword” piece, as well as on an ASN blog, “Is FD-SOI Cheaper? Why yes!”, (27 June ’14). However, in the end, he reminded readers that costs won’t be the deciding factor.
- FD-SOI: 20nm Performance at 28nm Cost by Paul McLellan (28 July ’14) covered a presentation given by Samsung’s Kelvin Lo about their foundry strategy at the CSPA (Chinese Semiconductor Professionals Association) meeting. Low reiterated that 28nm FD-SOI is the sweet spot for low-power, high performance. McLellan then briefly covered the Cadence quarterly conference call, which indicated interest in FD-SOI is up.
- FD-SOI Target Applications Are… by Eric Esteve (1 Aug. ’14) looked at the big picture. He had listened to the July ST analyst call, where they said they had 18 FD-SOI ASIC design wins.
- FD-SOI at 14nm by Paul McLellan (17 Aug. ’14) looks at an ST presentation given at SemiconWest in 2013 – a good overview with some pertinent technical detail.
Next, check out this interesting post in SemiconductorEngineering by Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. She gives a very informative perspective on “Power Reduction Techniques” (7 Aug. ’14) in bulk planar, FD-SOI and FinFETs. She talks about how biasing in FD-SOI is highly effective, then goes on to summarize various power-reduction techniques by process node. There’s an excellent summary in her graphic (her Figure 2):
There’s also a terrific chart in the same article based on the annual Synopsys’ Global User Survey (GUS), indicating which power techniques are used most in which applications (mobile, automotive, networking, etc.).
If talk on LinkedIn is any indication, the design community in India is very interested in FD-SOI. EE Herald published a much-shared interview with ST’s CAD/design solutions director in India (18 July ’14), entitled FDSOI; The only semiconductor tech to continue Moore’s Law down to 10nm. It gives an excellent overview of the technology, answering some of the basic questions designers are asking.
Finally, the folks at the silicon prototyping brokerage CMP pointed us at a bit of humor – and as they say, a picture’s worth a thousand words….