Synopsys recently announce that its IC Compiler II place and route solution was used by STMicroelectronics to tape out a complex 28-nm-FD-SOI SoC. (Read the press release here.) Fast throughput and analysis delivered a 10X reduction in time-to-good-floorplan. A 5X faster implementation with 2X smaller memory footprint enabled breakthrough productivity while exceeding quality of results (QoR) in area, timing and power goals.
Thierry Bauchon, ST R&D Director, said, “Our experience proved the promise we saw early in the design with 10X faster design exploration and 5X faster implementation, enabling us to refine floorplans, up-size physical partitions and achieve faster clock speeds on this tapeout.”
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