Heads Up! S3S (SOI+) Conference w/FD-SOI Design Short Course, 14-17 October 2019, San Jose

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R&D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.

The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam.

Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI.

Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):

Short Course Opening and Welcome
Philippe Flatresse, Business Development & Marketing Director, Dolphin Design

GLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies
Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIES

Embedded Flash Memory Technologies and Applications in Advanced Nodes Memories
Koji Nii, Vice President, Global Marketing & Sales, Floadia Corporation

Enabling the Adaptive Body Bias in Modern IoT Applications
Vincent Huard, CTO, Dolphin Design

SoC Design Realization with Adaptive Body Bias
Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics
Didier Roland, Application Engineers Manager, Mentor Graphics

Analog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion
Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R&D

Low Power Solutions for SoC Architectures
Antonio Pullini, Senior Hardware Designer, GreenWaves Technologies

SOI to RF
Sidina Wane, CEO, eV-technologies

If you know the way to San Jose, you’ll want to be at S3S 2019, for sure!

About the author

Adele Hars editor