The Compact Model Coalition (CMC) has selected Leti’s L-UTSOI as a standard model for FD-SOI in the industry. The CMC is a working group composed of the major semiconductor companies and is part of the Silicon Integration Initiative (Si2). The Si2 Compact Model Coalition announcement covers the approval and financial support of L-UTSOI.
L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years.
Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory, said the selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it. “This is of paramount importance for large chip makers who will use this model in the future,” he continued. “With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.”
Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models.
“As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer requests for model support as we continue to add value to their membership.”
Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, foundries, and IDMs. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications.
L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021.
“CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.”
As noted in Leti’s announcement (read the whole thing here), the FD-SOI transistor’s back-gate allows tuning of the device in a low-leakage and low-power operating regime or higher-performance operating regime. This unique capability offered by FD-SOI enables the fabrication of smaller, faster and denser chips than standard bulk CMOS technology. FD-SOI devices are widely used in wearable electronics, automobiles and IoT. Leti pioneered FD-SOI in 1992. Here at ASN we’ve been covering their FD-SOI compact model work for over a decade.