SOI News spoke with Philippe Berger, CEO of chip & silicon IP design / power management specialist Dolphin Design. Here’s what he told us about the work they’re doing on FD-SOI.
SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI?
Philippe Berger (PB): Low power is part of Dolphin’s DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies.
Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs.
FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip.
This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC.
We have two complementary offerings for companies that want to leverage FD-SOI:
The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage.
ASN: What’s driving that business?
PB: The emergence of new IoT and automotive markets is driving the business forcing IC design teams to pursue tough objectives: zero power consumption in off modes while maximizing the performance in active modes at minimal power consumptions.
Unfortunately, scaling down to the next technology node makes it even harder to reduce power in off modes and is an expensive choice – too expensive – for many applications to achieve the energy efficiency targets in active modes. As a result, design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the stringent requirements of the new IoT markets. This is particularly tricky in advanced IoT where near-sensor processing must be efficiently combined with RF connectivity, together with advanced power management. In addition, designers must confront the complexity of supporting high input voltage for interfacing with 4.2V/4.4V Li-Ion batteries or 5V USB charging mode that rely on 1.8V IO transistors.
The need for solutions that enable to select fast and to implement safely the power management network which allows a seamless system-level integration while meeting power consumption targets in each SoC power mode — that drives our business.
SN: What do you see as the biggest benefits – and challenges – for designers moving to FD-SOI?
PB: Its biggest benefit is its high integration capability. One of its key challenge is the ”so-far” relatively more complex design methodology that is required to take advantage of all FD-SOI characteristics, namely for example the biasing of the bulk to either reduce leakage or improve energy efficiency depending on working mode and technology centering. And ultimately, assuming the FD-SOI design flow is no longer a point of discussion, we need to get all designers “Thinking FD-SOI”. By that I mean to be aware of the breadth of FD-SOI advantages, so they are using it at every possible opportunity: in RF, in switches, in A/D converters (ADC) – in everything! FD-SOI’s double gate lets you think about more than decreasing noise and energy consumption. There are many opportunities for many blocks – especially analog. We need to get all designers “Thinking FD-SOI” so they’re using it at every possible opportunity: in RF, switches, ADC – in everything! Body biasing is usually thought of in the digital context, but it is also very useful in analog.… Click To Tweet
SN: What does Dolphin Design offer designers moving to FD-SOI?
PB: In order to ease these tasks, we developed the turnkey Spider platform based on power management IPs and system-level utilities. It speeds-up the design of energy efficient power management systems to weeks instead of months. Spider obviously exists in FD-SOI technology.
It enables chip-architects to explore many power architectures and to select the best one to match the targeted PPA. It bridges the complexity gaps of designing fast and safely a power controller that can deal with numerous power domains and several operation modes for each domain and that can operate even when the CPU is off. Then, it bridges the gap between standard RTL and GDS flow, as it is able to generate the UPF backbone of the SoC. It offers a standardized and predictable power management flow, securing first silicon success.
As an example, one of our key customers doing a ULP MCU shared that they have been able to design a complete power controller in less than one week instead of a couple of months.
SN: You announced design kits with Adaptive Body Bias (ABB) solutions for GlobalFoundries’ 22FDX technology at the end of 2019. What challenges is that solving?
PB: In the race for higher energy efficiency, digital designers face the impact of process variations. Chip designers have added margins all along their design to ensure the future chip will work fine whatever the technology centering after fabrication. Performance or size tradeoffs are necessary to cope with extreme variation cases (the so-called “corners”). At low voltage, SoC designers often use compensation techniques to limit the impact on the SoC energy efficiency.
Through the control of transistor threshold voltage in FD-SOI technology, body biasing acts as a fantastic and automated control method to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the PPA trade-off up to 10x at low voltage.
We have been cooperating with GlobalFoundries over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop. From standard-cell library to sign-off verification, our customers will continue to use their usual standard flow.
For IoT on GF 22FDX, the design kits are available for production. For automotive, it will be in the next months.
SN: Looking to the future, will there be a need for more application-specific FD-SOI IP? Where are the growth opportunities? Which ones will you be working on?
PB: We anticipate new needs along the time as new applications will emerge in FD-SOI. We have a roadmap to enrich the catalog of power management IPs for addressing each market vertical with the most complete offering.
But where we see the biggest growth for us is the growing adoption of power management IPs even by companies that were used to make voltage regulators on their own.
Power management is no longer an issue of designing some good voltage regulators, like LDOs. Fabless companies face the challenge of dealing with the growing complexity of SoC power management network. It absorbs a significant portion of their design “energy”, in logic and in analog domains. They need to customize voltage regulators for each SoC and to maintain their design to keep them competitive. They also face the challenge of complex and sensitive power controller design. Finding the right design expertise to make such complex SoCs is a challenge in itself and in many cases power management complexity is the cause of a design respin.
With the emergence of solutions such as Spider, that streamline and secure the selection and the implementation of the power management network, fabless companies start to question whether their core competency is power management IP design or if they can focus their design resources where they are the best at.
The addition of body biasing into this picture makes it even more obvious for fabless companies that relying on a solid IP partner is a strong option.
For Dolphin Design another opportunity for growth will mainly come from our capability to expand our offering for complementary design platforms for various FD flavors. We will communicate a lot in the coming months on our design platforms.
We are also looking for diversification to other SoC functionalities. Processing is definitely an area in which we are significantly investing (MCU sub-systems and their associated DSPs), but energy harvesting and RF could also be good candidates in the future.
SN: Dolphin Design is a member of the SOI Consortium. What do you see as the advantages of membership?
PB: The 2019 Silicon Valley SOI Symposium was my first participation in an SOI Consortium event. [Note: you can get his full presentation here.] My first impression was good! I was positively surprised by the wide diversity of material shown. But really the key advantage was the opportunity to meet with so many different companies, all involved, from near or from far, with an FD-SOI tape out. It really helped me understand what I needed to put my teams to work on next!