Soitec Characterization Lab

Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electr

EUROSOI

A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of m

EDS Honors SOI Pioneer

SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS device

SOI By the Book

A new book, SOI Device Technology by Makoto Yoshimi, PhD, covers the history of SOI, the floating body effect and a variety of LSI applications.

WORLD’S FIRST GaN-ON-INSULATOR

Here’s a quick review of some recent Smart Cut activity. March 2005 - WORLD’S FIRST GALLIUM NITRIDE (GaN)-ON- IN

SOI-MEMS in OIL EXPLORATION

While microelectronics relies on SOI for its insulating layer, SOI-MEMS benefits from the single crystal silicon of the top layer and substrate.

GaN On the Move

• High Growth Projected for GaN According to a recent report in “SST” magazine, the Silicon Valley-based market research firm Strategies U

45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI

The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a S

How to Use SOI for Low-Power Applications

SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already

A selection of recent papers of interest to the advanced substrates community.

• Soitec will have two invited and five contributed papers in the upcoming Silicon-on-Insulator Technolo