Here’s a quick review of some recent Smart Cut activity.
Soitec announced that its Smart Cut technology was used to split and transfer a thin layer of GaN from a high-quality GaN donor wafer onto a carrier wafer— generating the world’s first single- crystal, thin-film gallium nitride (GaN)-on-insulator substrate. This represents a critical step forward in enabling the development of high-performance blue and white light-emitting diodes (LEDs), as well as for improving current and future device performance in radio-frequency (RF) and discrete power applications Read More
While microelectronics relies on SOI for its insulating layer, SOI-MEMS benefits from the single crystal silicon of the top layer and substrate. A good example is the latest product from TRONIC’S Microsystems, a French manufacturer of high-end custom components.
The geophone, a seismic vibration sensor manufactured for Sercel (the world leader in oil exploration equipment), benefits from the latest advances in SOI micromachining to reach resolution (mechanical noise) as low as 0.1µG. (Please see www.tronics-mst.com for a full case study.) Read More
According to a recent report in “SST” magazine, the Silicon Valley-based market research firm Strategies Unlimited is projecting substantial growth for the gallium nitride (GaN) market. Worth $3.2 billion in 2004, the market is expected to increase to $7.2 billion over the next five years, making it one of the most successful compound semiconductor materials. The report, entitled “Gallium Nitride 2005 – Technology Status, Applications, and Market Forecasts”, says that white LEDs account for over half of the GaN-related LED market. It also sees big growth coming Read More
The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness).
The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors (planar & non-planar), ESD structures, Kelvin structures and various test circuits (Ring Oscillators, loaded gates, Current Mirrors, OP-AMPs, SRAM cells, and reliability test sites). Read More
SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications.
When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to:
• the combination of a lower junction capacitance,
• an increased drive current during transition of the gates due to dynamic capacitive coupling
• and an improved drivability of gates using stacked transistors (NAND, NOR, etc.). Read More