Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electr
A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of m
SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS device
A new book, SOI Device Technology by Makoto Yoshimi, PhD, covers the history of SOI, the floating body effect and a variety of LSI applications.
Here’s a quick review of some recent Smart Cut activity.
March 2005 - WORLD’S FIRST GALLIUM NITRIDE (GaN)-ON- IN
While microelectronics relies on SOI for its insulating layer, SOI-MEMS benefits from the single crystal silicon of the top layer and substrate.
• High Growth Projected for GaN
According to a recent report in “SST” magazine, the Silicon Valley-based market research firm Strategies U
The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a S
SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already
• Soitec will have two invited and five contributed papers in the upcoming Silicon-on-Insulator Technolo
© SOI Industry Consortium 2019