Two of the big, recent breakthroughs in memory technology – eMRAM and ePCM – have gotten their start in volume manufacturing on 28nm FD-SOI. In conjunction with the 2019 IEEE International Memory Workshop, SOI Consortium members Leti and Applied Materials have teamed up to give a technical program to explore short-term and long-term memory solutions. While the workshop is not specific to SOI, given the recent foundry announcements about ePCM and eMRAM for FD-SOI, the organizers predict it will be of particular interest to those following the greater SOI ecosystem. The event takes place at the end of the Sunday IMW tutorial day, starting at 5:30pm at the Hyatt Regency in Monterey, CA. Please see this page for the program and registration information.
Here is the program:
Jean-Eric Michallet, Head of Leti’s Microelectronics Components Department, Silicon Component Division is one of the organizers. Here is his overview:
FD-SOI is expected to be a long-lived technology. It enables planar CMOS scaling and accommodates a great deal of More-than-Moore developments where its ability for low power and great analog performance can make a difference for IoT, Automotive, Machine Learning or 5G applications. But to do this it requires a high-performance and cost-effective non-volatile embedded memory option. The incumbent Flash cell is reaching the end of its roadmap due to the difficulty of shrinking the bitcell and manufacturing, as well as the finished wafer cost increase. Back-end integrated Random Access Memory in advanced CMOS process has been explored for many years now as a competitive solution for fast-write and low-voltage non-volatile embedded memories. Foundry availability of embedded Magnetic RAM and Phase Change RAM for FDSOI 28nm platforms has been announced recently, showing that these technologies have now reached industrial maturity. CEA-Leti and Applied Materials invite you to attend a technical program to explore short-term and long-term memory solutions, from early research to industrialization.
Registration is open, free, and available to all IMW attendees, and others. However, as seating is limited and as we have already several participants pre-registered, registration is by invitation only and early registration is recommended. If you are interested, please email Jean-Eric Michallet.
The event is presented in conjunction with the 2019 IEEE International Memory Workshop, to be held on Sunday, May 12th, 2019, Hyatt Regency, Monterey CA, starting at 5:30 pm.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
Une interview de Carlos Mazure, CTO de SOITEC et Président du SOI Industry Consortium
Une interview de Jean-Éric Michallet, responsable du département micro-électronique du LETI
FD-SOI for RF and mmWave communications is a hot topic. In high-data rate communications like RF and millimeter-wave devices in particular, FD-SOI delivers high-performance with numerous unique advantages, making it most likely the fastest RF-CMOS technology on the market.
If you’d like to take a deep dive and learn more about it, Soitec and Incize are sponsoring a free, full-day workshop in Grenoble on April 4th, 2019. Click here for registration information. The workshop follows the day after the IEEE/EDS EuroSOI-ULIS conference there (you can read about the full conference in a previous ASN post).
This technical workshop will cover the FD-SOI technology platform with a focus on its compatibility with RF & mmWave communications. Attendees will hear from notable FD-SOI leaders and experts from leading industry and research institutions presenting updates on key developments and building blocks across the semiconductor value chain. Topics will include circuit design, device fundamentals, simulation and characterization of RF devices, test, CMOS technology and substrate technologies enabling FD-SOI. In addition, the workshop will include an overview about how FD-SOI technology is benefiting current and future end user applications.
Here’s the agenda:
Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.
IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.
Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.
The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.
I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.
I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.
One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.
Mark provided a GF link for more information:
Here is the link to our Automotive resources:
One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.
Here is the press release:
Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process
Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs
MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.
“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”
“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”
“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:
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About the Author
Daniel Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”. He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.
The world’s SOI wafer leader, Soitec is posting strong sales and issuing a steady stream of compelling announcements. This is clearly good news for everyone in the SOI ecosystem, as the outlook for the various families of SOI wafers is excellent.
Soitec CEO Paul Boudre told ASN, “I’m excited because of the fundamentals behind the growth. Reaching down the supply chain gives us the ability to help our customers with the next generation. We’re not in a technology push, but in a technology pull. It’s long-term growth we’re seeing.”
Soitec has brought people from the device side into the company to better understand the solutions customers need, he said. They’re talking to the carmakers, telcos and more, working one-on-one with them to understand the constraints and the problems they are trying to fix, in order to deliver a solution based on the Soitec product roadmap. Boudre is particularly excited about 5G. It’s not just new handsets and systems: the entire infrastructure will require a massive upgrade, across which Soitec has a role to play supplying SOI wafers.
They also have other SOI and engineered substrates for specific markets like filters, displays, imaging and power. He adds that they’re seeing nice growth in SOI wafers for photonics, driven by cloud computing, and for smart power in markets like automotive and white goods.
Here’s a roundup of some recent developments. Chips made on RF-SOI wafers are in every mobile phone made on the planet these days, so lets look at what they’re doing there first. We’ll follow that with an update on the surge of activity on FD-SOI wafers.
It’s no secret that the runaway success of RF-SOI for front-end modules (FEMs) in mobile phones has stretched wafer capacity mightily. To help address this, in February 2019 Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. The two companies redefined their manufacturing and licensing relationship to better serve to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics.
Since the two companies signed their original licensing and technology transfer agreement in May 2014, Simgui has mastered Soitec’s Smart Cut™ proprietary process to deliver world-class RF-SOI and Power-SOI products. Simgui’s strategic partnership with Soitec allows them to use the same tools and processes to deliver the same products meeting the same specifications.
Simgui has invested in their Shanghai fabrication line in order to double annual 200mm SOI wafer production capacity from 180,000 to 360,000. The fab is production ready, having been qualified by multiple key customers inside and outside China.
Simgui CEO Dr. Jeffrey Wang notes, “China has design, wafer manufacturing and good momentum in the IC industry. We are committed to our strategic partnership with Soitec to keep advancing SOI as China’s key differentiator.”
China Mobile’s interest in the SOI ecoystem is clear: they’ve presented at the SOI symposia in Shanghai for two years running now. In a February 2019 press release, Soitec announced that they’ve joined the China Mobile 5G Innovation Center – and they’re the first materials supplier to do so. The China Mobile 5G Innovation Center is an international alliance chartered to develop 5G communication solutions for China, the world’s largest wireless communications market with 925M mobile subscribers. The Center aims to accelerate the development of 5G by establishing a cross-industry ecosystem, setting up open labs to create new products and applications, and fostering new business and market opportunities.
Soitec’s RF-SOI wafers have been critical in the deployment of 4G communications, and the opportunity in 5G is even bigger. Plus the company’s FD-SOI wafers enable the technology that brings unique RF performance, making it an ideal solution for many applications including mmWave communications such as 5G transceivers. They are also enabling full RF and ultra-low-power computing integration for IoT and edge computing.
In January 2019, Soitec announced that they have expanded their collaboration with Samsung Foundry on the FD-SOI wafer supply, securing the high-volume Samsung needs to meet industry’s current and future demands in consumer, IoT and automotive applications. The agreement is built on the existing close relationship between the companies and guarantees wafer supply for Samsung’s FD-SOI platform starting with the 28FDS process.
“Samsung has been committed to delivering transformative industry leading technologies,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “FD-SOI is currently setting a new standard in many high-growth applications including IoT with ultra-low-power devices, automotive systems such as vision processors for ADAS and infotainment, and mobile connectivity from 5G smartphones to wearable electronics. Through this agreement with Soitec, our long-term strategic partner, we hope to lay the foundation for steady supply to meet high-volume demands of current and future customers.”
“This strategic agreement validates today’s high-volume manufacturing adoption of FD-SOI,” said Christophe Maleville, Soitec’s Executive Vice President, Digital Electronics Business Unit. “Soitec is ready to support Samsung’s current and long-term growth for ultra-low power, performance-on-demand FD-SOI solutions.”
In February 2019 Soitec announced they’d become a strategic partner in Silicon Catalyst’s start-up incubator. Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses.
Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.
“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions.”
Pete Rodriguez, CEO of Silicon Catalyst said, “Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog/mixed-signal performance.”
And finally, jumping back a few months, at the end of 2018 Soitec announced that their SOI wafers are at the heart of a new Renesas SOTBTM energy harvesting chipset, opening a self-powered future for IoT devices. SOTB is how Renesas refers to its FD-SOI technology.
(BTW, here at ASN we’ve been covering the work that Renesas has quietly done on this technology since 2005 (!). And we did a piece about an EETimes Japan article back in 2015 that revealed the launching of the 65nm work. )
Soitec supports the Renesas SOTB chipset with a special version of its FD-SOI wafer product line. The new Renesas SOTB-based chipset overcomes the energy constraints of IoT devices and reduces the power consumption to approximately one-tenth that of the existing products in the market today. That makes the chipset perfectly suited for extreme low-power, maintenance-free and energy harvesting applications including wearable devices, smart home applications, smart watches, portable appliances, infrastructure monitoring systems, industrial, business, agricultural, healthcare, as well as health and fitness apparel, shoes, drones and more.
Renesas has developed its energy harvesting chip using its unique SOTB 65nm process technology that achieves both low active current of 20 μA/MHz and deep standby current of 150 nA. As a result, Renesas’ SOTB chipsets offer enhanced control of the transistor electrostatics and reductions in both the standby and active currents to levels never before achieved. Additionally, Renesas has successfully delivered the dopant-less channel to suppress Vth variability for the ultra-low voltage operation, and the ultra-low power back bias control to reduce the standby current at the same time.
“To spur innovations in IoT and consumer applications, we have integrated our exclusive energy-harvesting SOTB technologies into our Energy Harvest Controller,” said Mr. Toru Moriya, Vice President of Renesas’ Home Business Division, Industrial Solutions Business Unit. “We are confident that our SOTB technology built on Soitec’s ultrathin substrates can deliver unmatched capabilities for developing maintenance-free IoT devices that never require power supply or replacement, giving rise to a new IoT global market based on endpoint intelligence.”
The new R7F0E Embedded Controller is the first device based on Renesas’ SOTB technology. Developers can now design applications that need no battery or recharging. The R7F0E features: an Arm® Cortex® -M0＋; operating frequency up to 32 MHz, and up to 64 MHz in boost mode (that’s body bias in action!); memory of up to 1.5 MB flash, 256 KB SRAM; and active current consumption while operating at 3.0V of just 20 µA/MHz, and in deep standby of 150 nA with real-time clock source and reset manager. As of this writing, Renesas indicates it’s engaging select customers through July 2019, with mass production in 4Q19. Read more about the R7F0E on the Renesas website.
GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019.
As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.
The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.
“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”
“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”
As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of.
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*A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago:
Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.
For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering’s Ann Steffora Mutschler from a couple years ago.
STMicroelectronics is now sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on ePCM to alpha customers. Field trials meeting the requirements of automotive applications and full technology qualification are expected in 2020. These MCUs—the world’s first to use ePCM, which stands for embedded Phase-Change Memory—will target powertrain systems, advanced and secure gateways, safety/ADAS applications, and Vehicle Electrification. (Read the full press release here.)
“Having applied ST’s process, design, technology, and application expertise to ePCM, we’ve developed an innovative recipe that makes ST the very first to combine this non-volatile memory with 28nm FD-SOI for high-performance, low-power automotive microcontrollers,” said Marco Monti, President Automotive and Discrete Group, STMicroelectronics. “With samples already in some lead-customers’ hands, we’re confirming the outstanding temperature performance of ePCM and its ability to meet all automotive standards, further assuring our confidence in its market adoption and success.”
ePCM presents a solution to chip- and system-level challenges, meeting automotive MCU requirements for AEC-Q100 Grade 0, operating at temperature up to +165°C. In addition, ST says its technology assures firmware/data retention through high-temperature soldering reflow processes and immunity to radiation, for additional data safety.
Architecture and performance benchmark updates were presented the most recent IEDM (December 2018 in San Francisco) in a paper entitled Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory (F. Arnaud et al). As of this writing, the IEDM 2018 papers are not yet posted on the IEEE Xplore Digital Library site. However, the ppt that ST presented at the conference is available here.
For more in-depth information on ePCM, see the ST PCM page. To learn more about how it compares with competing technologies such as eMRAM, read Embedded Phase-Change Memory Emerges by Mark Lapedus of SemiEngineering. Papers describing other eNVM solutions on FD-SOI were also presented at IEDM 2018. Samsung’s is entitled Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic (Y. J. Song et al). GlobalFoundries’ is entitled 22-nm FD-SOI Embedded MRAM Technology for Low-Power Automotive-Grade-1 MCU Applications (K. Lee et al).
It should be a good year across the SOI ecosystem, with new products, players, IP, technologies and tools — and high volumes.
What’s new? Let’s start with the people, as the Consortium welcomes new team members. Jon Cheek of NXP will join Carlos Mazure as Executive Co-Director. He’ll be replacing ST’s Giorgio Cesana in that role – and goodness knows those are some big shoes to fill. Giorgio has given of his time and expertise so tirelessly over many years. He’ll of course still be a key resource for the SOI ecosystem, and though we’ll miss him here at the Consortium, we know he’ll be doing great things in SOI at ST. So a heartfelt thanks to Giorgio Cesana from all of us.
Jon Cheek has a long history in engineering management at companies that have been leading users of SOI: AMD, Freescale and now NXP. As such, he understands what companies need to design great products, and how the Consortium can help further build, promote, connect and support the ecosystem. The Consortium team also welcomes Jean-Eric Michallet of Leti, who’ll bring deep bizdev expertise and a keen sense of what it takes to reach further into the ecosystem. (Astute long-time ASN readers might remember his post from five years ago about 3D monolithic integration – now dubbed “Cool Cube” by Leti.) And finally, look to hear more from and about the Consortium, as our team is rounded out with the addition of the comm & marketing savvy of Erin Berard of Soitec.
In addition to new team members, the Consortium is very pleased to welcome new member Applied Materials. Though new to the Consortium, AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a consortium member is clearly a fabulous addition.
2019 will also be marked by the expansion of the highly successful SOI Academy series, the first of which was held this past fall in Shanghai. We’ll keep you posted as these and other Consortium events are announced throughout the year. In fact, 2019 marks a decade of (excellent!) SOI Consortium events events around the world: our first symposium was held back in 2009. Kicking off this year, save April 9th on your calendar for our Annual SOI Silicon Valley Symposium. Then watch this page for more events across the globe.
What will the year bring? On the product side, RF-SOI for 5G is of course super hot. Last summer, a SemiconductorEngineering headline proclaimed RF-SOI Wars Begin. And what we heard at the International RF-SOI Workshop last fall in Shanghai (presentations here) certainly confirmed that in the coming year the race will continue unabated.
And for FD-SOI, you might want to read the SE series published over the last six months. The latest, published a couple of weeks ago looks at FD-SOI at the Edge. There are some great insights from SOI Consortium members there. In terms of products, too, there’s lots of activity.
Last summer, Samsung indicated they’d taped out over 60 products since they first began offering 28FDS three years ago. It’s a trend they see accelerating. Full production of 18FDS is slated for this fall.
And also last summer GlobalFoundries indicated they had over 50 client designs on 22FDX. “We’re only just beginning,” said GF CEO Tom Caulfield at the time. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. ”
For its part, ST, as we learned at the last SOI Consortium Japan Workshop, has been doing FD-SOI for five years now. And while we don’t have number, we learned that some of those products are now in their second and third generations, and that some big FD-SOI chips coming out this year with embedded memory and RF, with especially good traction in mmWave, automotive and IoT.
So while the outlook for the overall industry is anyone’s guess for the coming year, the outlook for chips built on SOI technologies is very good indeed.