Although Intel will do FinFETs at 22nm, FD-SOI remains the better alternative for most all the industry for low power and mobile apps. In the weeks and months to come, we’ll continue hearing the SOI camp addressing key points.
1. FD-SOI technology is the most cost-effective solution. The wafers are available from multiple sources. With volume purchasing, multiple mask layer savings and evolutionary design transition, FD-SOI comes in cheaper.
2. Ultra-thin SOI wafers are ramping in volume this year. Although for years, it was thought SOI wafers with super thin top silicon and BOX were beyond the purview of suppliers, Soitec has done it using their standard Smart Cut wafer manufacturing technology. These wafers are available now (see the ASN16 article where Soitec gives the details). Manufacturing lines are set to roll with industry ramp.
3. The ultra-thin SOI can include ultra-thin BOX. Much of FD-SOI will use ultra-thin BOX as well as ultra-thin top Si. ST is an example of a company doing great things here. As they pointed out in a recent ASN article, “Designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.” The ultra-thin BOX and ground plane with or without bias enables this option with a simple process flow. Their hybrid co-integration approach on ultra-thin Si/BOX SOI lets them reuse bulk ESD and I/O IP.
4. FD-SOI does very well for both performance and power savings – at high and at low voltages. The supply voltage (Vdd, which essentially determines power consumption) is different depending on the app and the state of the device. Intel says its TriGate gets a 37% propagation time improvement (therefore enabling improvement of operating frequency by 58%) over the previous generation at 0.7V; but FD-SOI is getting a +125% operating frequency improvement. The SOI Consortium recently published data about FD-SOI on an ARM chip. Now they’re working on further data, and on lining up the ecosystem.
For the real world of high-performance, low-power mobile apps, planar FD-SOI really looks like the way forward. For those in the fabless world, it gives game-changing results without changing existing design flows or manufacturing processes. The SOI Consortium has a terrific Q&A if you need more about planar-FD-SOI in general.
Intel does amazing things on the fab floor, to be sure. But the FD-SOI camp has done the math, too – and they’ve got a very different story to tell. Watch this space!
Microsoft and IBM moved the CPU and the GPU of the best-selling game console in North America onto a single SoC – a year ahead of the pack.
There’s a lot of excitement about the “latest trend” of integrating both the computing chip – the CPU and the graphics chip – the GPU – into a single chip. But in fact, the first GPU/CPU system-on-chip (SoC) came out in June 2010. It’s on 45nm SOI, is produced by multiple foundries, and is at the heart of the hottest selling game console in North America: the Xbox 360.
The technical community refers to it as the Xbox 360 S – “S” for “slim”, because the new chip enabled a host of slimming effects. The two most important were a slimmed-down power budget (43% less than the previous generation) and a serious reduction in the bill-of-materials (always good news for the bottom line).
You might think that the GPU/CPU combo also provided a major performance boost. But in fact, for game console lifetimes, one thing you can’t do is toy much with performance. Game developers count on having a stable platform – they need it to work just the way they first planned it for the entire console life cycle.
One of the advantages SOI gives to chip designers is that it’s a powerful “knob to turn” – they can ratchet up performance (and keep about the same some power budget), or drastically reduce power (in exchange for a less dramatic performance increase), or they can find a balance somewhere in between.
In the case of the Xbox 360 GPU/CPU, one can surmise that since they couldn’t boost performance too much, they had the luxury of turning the knob way down for power. And that translates into a whole lot of benefits.
But first let’s look at what they actually did.
The first Xbox 360 came out in 2005, with a CPU on 90nm SOI (see ASN #6) and a GPU on 90nm bulk. A few years later, the chips were migrated to 65nm. Then in 2010, the two were combined on a single chip using 45nm SOI.
For the IBM and Microsoft chip design team, the latest challenge involved both a port (the bulk GPU to SOI), a shrink (to 45nm) and a complete redesign of the GPU (which had originally been designed by ATI). However, from a graphics standpoint, the resulting chip had to remain functionally identical to the old GPU, to ensure the backward compatibility of the games.
It also involved removing the front-side bus (FSB), which handles functional intercommunication between the CPU and GPU blocks.
Compared to having two chips, putting the two units into one chip saved 60% in power and 50% in area compared to the 90nm versions.
In terms of silicon, the savings are obvious when you’re fabbing one chip instead of two. However, the ramifications for savings extend far beyond the silicon.
Consider thermal design, for example. Instead of cooling two chips, you just have one: so one heatsink; one fan. And with good thermal management, the fan speed is lower – so it’s significantly quieter and needs less power for the fan.
This simplifies the motherboard layout and power delivery. And of course, between the lower power chip and the slower fan speeds, they could use a smaller power supply unit.
All these factors combined to enable a reduction in console size. However, the new chip is robust enough to also seamlessly handle the high-performance processing for Microsoft’s Kinect – the new motion sensor that replaces the controller.
In January 2011, Microsoft announced that the new Xbox 360 had just capped off six consecutive months as the best-selling console in North America. More than 50 million Xbox 360 consoles have been sold worldwide – double the amount of the previous generation Xbox.
Sales are up 27% year on year, and Microsoft has indicated that this console should keep going strong through 2015. Which shows that great things happen – and keep happening – on SOI.
A special thanks to Bob Drehmel of IBM for his technical guidance on this article.
In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions.
MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate.
One of my favorites is Debiotech’s tiny insulin NanopumpTM targeting diabetes, fabbed by ST. As Debiotech’s Laurent-Dominique Piveteau noted, “…the use of SOI wafers for fabricating the Nanopump MEMS device has significant medical and economic advantages. The SOI-based structure allows for the highest reliability in the smallest possible package, enabling very tight control and precision of the pumping mechanism. The flow rate is steady, and it is insensitive to pressure, temperature, viscosity and aging. It also offers extreme dosing precision.”
Reasons cited by other contributors for using SOI for MEMS include:
But the bottom line is that it’s the most cost-effective solution for their state-of-the-art MEMS devices.
MEMS also figure in two of the most recent ASN Buzz postings:
In the next few weeks, we’ll also be posting a new article by Soitec on their Smart Stacking(tm) technology for the next generation of MEMS with pre-etched cavities, among other things.
If you’d like to see more of the why’s and wherefore’s of SOI-MEMS apps, just type “MEMS” into ASN’s search engine. You’ll get dozens of pieces from and about leaders like ST, ADI, Denso, VTI, Tronics, IBM and more.
It’s a pretty fragmented world, still, so if you know cool SOI-MEMS apps we should be covering, would you let me know?
The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront.
As always, performance gains generate plenty of buzz. But the SOI papers were also notable for work reducing power consumption, extending scalability and overcoming threshold voltage variation.
IBM presented the world’s highest frequency microprocessor to date, clocking in at 5.2 GHz. On 45nm SOI, it’s the first commercial processor ever to break through the 5GHz speed barrier, and is the centerpiece of Big Blue’s new zEnterprise 196 system.
In another paper, IBM presented the first embedded high-k/metal-gate (HK/MG) SRAM on 32nm SOI enabling operation at down to 0.7V.
AMD presented its Bulldozer 2-core modules, which are on 32nm SOI with HK/MG. Clocking in at 3.5GHz, we’ll see them beginning in desktop and server Fusion chips this year.
In a quieter but clearly significant paper, ST and Leti compared 65nm low power (LP) partially depleted (PD) SOI with standard 65nm LP CMOS bulk. They found that PD-SOI, when combined with a low resistivity produced with forward body bias of the power switch, can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.
For summaries of additional SOI-based papers at ISSCC and other recent conferences, see ASN’s PaperLinks.
Up to 80% additional performance improvement on an ARM Cortex M0. 40% lower power for SRAMs. These are the amazing planar FD-SOI results just announced by the SOI Consortium. Things are suddenly looking much brighter in the world of low-power, high-performance chips for mobile and consumer apps.
An A-list of companies collaborated on this assessment/characterization – ARM, GlobalFoundries, IBM, ST, Soitec and Leti – so you know the results are really solid. People want PC performance in a cell phone (without having to recharge the battery three times a day, thank you!). These guys know what it takes to make the chips that can make it happen.
For designers and manufacturers, FD-SOI is a win-win: design flow is the same as bulk, so there’s no learning curve; manufacturing is vastly simplified, so it costs less.
Let’s make a few things clear here: that +80% – that’s on top of the +25% improvement you’d get moving from one node to the next. So if you move to FD-SOI at the same time you’re moving down a node, you can get (do the math) a +125% (!!) improvement in performance – and lower power. Designers sweat blood for a few percentage points of performance improvement, and here you get more than double – and it’s cheaper and easier. Wow.
The 40% power savings on the SRAM (which now typically accounts for over half the chip) – that’s because with FD-SOI you can run it reliably at lower voltages – which of course saves battery life.
It’s worth pointing out that much of this success is due to some amazing work by Soitec. Their R&D folks first wrote about the ultra-thin wafers needed for FD-SOI in ASN five years ago. They’ve been working on perfecting those wafers ever since – and supplying them to the IDMs and foundries for some time now, so those guys could get on with their early legwork. The requirements for silicon and BOX layer thinness and smoothness are draconian: we’re deep in the world of Angstroms here.
All the while, there were some hefty naysayers claiming the wafer requirements could never be met. But guess what: those requirements have been met – and the wafers are ready to roll.
I urge you to read Christophe Maleville’s article in our most recent edition: Wafers for Fully-Depleted Devices: Ready for Volume – and look at the all the checkmarks on that list of requirements. It’s really some impressive work.
So, want to know more FD-SOI? Let me point you at some sources:
Planar FD-SOI: it’s the start of something big.
The AMD PR folks are calling their new Fusion APUs the era of “Personal Supercomputing” – and its flagships are on 32nm SOI We’ve been hearing about these revolutionary chips for years now – the “Fusion” of graphics chips – GPUs – and CPUs on a single piece of silicon, which they’re referring to as an APU – an “Accelerated Processing Unit”.
Launched last week at CES in Las Vegas, the SOI-based “mainstream platform” is primarily intended for performance and mainstream notebooks and mainstream desktops. First up is the 32nm die A-Series “Llano” APU, which includes up to four x86 cores and a DirectX 11-capable discrete-level GPU. It’s scheduled to ship in the first half of 2011 and appear in products mid-year.
Now, with a bit of detective work, we can sort out the SOI-based APU roadmap that AMD announced at its Financial Analyst’s Day in November 2010.
AMD divides its roadmap into “Notebooks”, “Desktop” and “Server”. Here’s what to look for on 32nm SOI.
Notebooks – CPU/APU Roadmap:
Desktop CPU/APU Roadmap:
Server CPU Roadmap:
GlobalFoundries is of course the fab – debuting 32nm SOI with high-k/metal-gate (HK/MG). Here’s what CEO Doug Grose showed financial analyst’s at the end of 2009 (yes, so you can tell any doubters that GloFo was already showing great HK/MG 32nm SOI over a year ago!):
And here’s what Chekib Akrout, senior vice president and general manager, AMD Technology Development, showed the financial analysts in November 2010:
Very cool stuff. What do you think? Will it find its way into your products or onto your desktop this year?
Then of course there’s all these changes in the upper echelons of AMD management that transpired this week, plus the Intel/nVidia settlement. What does your crystal ball say about all that? Leave a comment and let us know.
(All images courtesy of AMD.)
“SOI SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA),” says ARM SOI guru Jean Luc Pelloie.
With that in mind, the ARM team presented a quiet paper at the last IEEE SOI Conference (Oct. 2010) – but one that has important implications for the industry. “Timing Verification of a 45nm SOI Standard Cell Library” is not yet available on the IEEEXplore site, but Jean Luc summarized the key points for Advanced Substrate News (ASN) (see http://www.soiconsortium.eu/2010/12/right-timing/).
The take-away message: “It’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.”
The history effect is just another “corner”. Since it’s accurately accounted for in the physical IP libraries, it’s pretty much transparent in the design flow, he explains.
On the foundry side, says Jean Luc, ARM is helping leading foundries retune their 45nm SOI SPICE models for greater accuracy.
If you’re a designer, is the history effect something that still concerns you? Does this news make you feel a little more sanguine about diving in to SOI? Leave a comment and let us know.
(BTW, ARM’s been a regular contributor to ASN – see http://www.soiconsortium.eu/pages/companies/arm/ for more.)
For five wonderful years, we’ve had a terrific paper and electronic version of Advanced Substrate News – aka ASN – bringing you must-read pieces from in and around the SOI and engineered substrates ecosystem. That’s not going to change.
We’ve had hundreds of articles contributed by experts from all walks of industry and academia. That’s not going to change.
We’re your source for everything SOI. That’s not going to change.
What’s changing is our website. In addition to carrying both the latest and archived versions of ASN, we’re adding a new, dynamic dimension. Which stands to reason – SOI has moved into high gear, so we are, too.
We’ll be updating regularly, with an Editor’s Blog, the latest IndustryBuzz, PaperLink highlights from recent conferences and more. When you read one of our pieces, we can now invite you to leave your comments.
To keep up with us, you can follow via Twitter, email alerts, RSS feeds, or LinkedIn.
We’re very excited to offer this great new change to the SOI and advanced substrates community.
Of course, if you’re already on our mailing list, you’ll continue to receive the latest editions of ASN, which we’ll still be publishing throughout the year. (That’s not going to change!)
Start by checking out ASN #16, featuring SOI’s leading role in the lighting revolution, and the availability of amazing ultra-thin wafers for FD-SOI.
Do you like it? Did you learn something? Are there articles you want to share with colleagues? Then click now to tell us what you think – and don’t forget to post, re-post, tweet or re-tweet.
With many thanks and best wishes for a safe, innovative and Happy New Year.
SOI is poised to take center stage in the impending lighting revolution, with companies like NXP leading the charge. Here’s why.
Incandescent bulbs are being phased out or banned worldwide: European bans started taking effect in 2009; the US, Canada, Japan and Russia will start in 2012. India, Brazil, China and many more have all taken action.
Compact Fluorescent Lamps – CFLs – are poised to take the relay in the short term, followed later by LEDs (as they become more cost-competitive).
But consumers are in an uproar about the quality of most CFL lamps – and with good reasons: even though 4 billion a year are sold, they’re usually too slow to get up to full brightness, they don’t last as promised, they’re expensive, the color’s cold and unfriendly…and so the list goes on.
Lighting designers need chip solutions that solve these challenges without compromising time-to-market and cost. With SOI-based processes, lighting components leader NXP’s got the answer.
But to understand these challenges, it helps to understand a few basics about CFL lighting technologies past, present and future.
The meaning of “incandescent” is to produce light by heat. The modern incandescent light bulb, with its swirl of tungsten filament, has been doing that more or less unchanged in our homes for the last 100 years.
Electricity enters the bulb on a metal wire, comes up against the resistance of the tungsten (also a metal) filament, causing said filament to glow: ie. produce light. But it does this very inefficiently: only about 10% of the energy going in to an incandescent bulb comes out as light; most is dissipated as heat. The rule of thumb is that it takes an incandescent bulb one watt to produce around 15 lumens of light, so a 60-watt bulb produces about 900 lumens.
The fluorescent light – and its more recent incarnation, the CFL – works on a very different principle. Essentially, you have to get electrical current flowing through a tube containing mercury vapor and coated on the inside with a phosphor. The electrons around the mercury atoms get excited by the current, jumping into higher orbitals then dropping back, thereby releasing ultra-violet (UV) photons (which are invisible). These UV photons in turn excite the phosphor, which emits visible light photons.
With just one watt, a CFL can produce 50-70 lumens. So, to produce 1000 lumens takes the CFL as little as 20 watts.
It sounds straightforward, but when it comes to making light with electricity, gas has one very different characteristic from metal. Metal – the heart of incandescent lights – is by its very nature resistant. And the resistance in metal is very constant and predictable – affected only by the kind of metal, how thick it is, and temperature.
With gas, however, the more current you run through it, the more it loses its resistivity. If you were to just plug a fluorescent tube into the mains, the amount of current flowing through the gas would quickly climb and climb til the bulb – literally – blew out. So you have to control the current very carefully: this is where ballasts come in.
All fluorescent lamps must have ballasts at the ends of the tube, which get the current flowing through the gas and then control it. Old fluorescent lamps where not terribly good at this. They had a complex preheat system to ionize the gas in the tube and get the current flowing. But those old ballasts were based on electromagnetics (think: wire coils): the unsteady current produced those awful flickering, humming fluorescent lights of our childhood.
To make fluorescent bulbs that would fit into the same size light sockets as incandescents required a much smaller solution. Enter the electronic ballast: a little circuit board with independent passive and active components, including rectifiers, capacitors, switching transistors and inverters. They have to kick off with a very high-frequency jolt of electricity – about 40,000 Hz to ionize the mercury vapor – then settle right back to a normal operational levels (such as 50 Hz in Europe, 60 Hz in the US).
However, one of the challenges for lighting product and electrical design engineers is that the circuitry in each ballast has to be custom-tailored to the shape and size of each CFL tube design, with all its twists and turns.
NXP recognized that integrating as many of the discrete components of a light ballast as possible into a single driver IC could drastically simplify lighting ballast design while improving overall system performance (lifetime, form factor, switching cycle) and quality (reliability, robustness, early failure, and so forth).
A driver IC bridges the analog and digital worlds, taking a logic signal output from the control system’s microcontroller (which can be integrated onchip or can be on a separate chip), and provides the appropriate current and voltage to turn power devices on and off. As such, it has to be extremely robust – especially in a high-temperature environment – yet very cost-competitive.
Leveraging its EZ-HV SOI technology (see sidebar), NXP is integrating an increasing number of components into high-voltage power ICs intended to drive and control electronically ballasted CFLs with few external components needed.
For example, the NXP UBA2024 family and its newly release successor, the UBA2211, is a 550 V lamp controller and half-bridge IC.
The high level of integration reduces the number of external components to only 17 (compared to the 27 typically required by a discrete driver solution). The IC supports NXP’s patented preheat and a series of protections, which the company says enables CFL lamps to reach lifetime performance of up to 15,000 hours.
As of 2009, lighting components market leader NXP had sold 300 million fluorescent lighting driver ICs. Now with regulations taking effect worldwide over the next few years, the market is set to explode.
“With 20 to 25 percent of the electricity produced in the world consumed in lighting applications, and over 5 billion energy saving bulbs to be sold in 2012 according to Datapoint Research, NXP’s next generation of CFL lighting drivers break open the next ‘killer application’ for power management ICs. Backed by [SOI-based] GreenChip technology, and NXP’s ability to manufacture to scale, the economics are staggering,” says John Croteau, senior vice president & general manager, Business Lines High Performance RF, Power & Lighting, NXP Semiconductors.
That certainly makes for a very bright, SOI-enabled future.
First announced a decade ago, NXP’s EZ-HV™ is process technology for the production of commercial high-voltage (HV) SOI-enabled ICs. It is at the heart of NXP’s GreenChip technology, and is ideal for implementing optimal solutions for a wide range of lighting applications. In high-power systems, it allows sophisticated control logic and high voltage drive circuits to be integrated into a single IC (replacing the separate high and low voltage chips), halving the cost of the overall unit.
It represents a radical departure from “thick SOI” solutions, in which a 10 to 20 micron layer of silicon overlaying an insulating material limits the electric field strength to prevent a regenerative, killer effect called ‘avalanche breakdown’.
Instead, the EZ-HV process uses SOI wafers with a relatively thin layer of top silicon (only 0.5 microns thick), which is much cheaper to produce. Even with 650 volts applied across this layer there is still insufficient distance between the upper and lower layers of the silicon for charge carriers to be accelerated to avalanche breakdown energy levels.
Other advantages include:
NXP’s UBA2211 for the 230V and 110V markets is the latest driver IC family in the company’s CFL IC portfolio. Built on NXP’s EZ-HV SOI technology, it features the highest level of integration available on the market today, including a current controlled preheat function, enabling more compact designs, highly efficient power conversion, and extended CFL lifetimes in the range of 12,000 to 15,000 hours.
“As incandescent bulbs are phased out around the world and with the recent EU ban on 75W incandescent bulbs in effect, the time is now for CFLs to prove they can offer better quality of light at lower costs. NXP driver ICs such as the UBA2211 offer breakthrough quality, performance and features that enable CFL manufacturers to match consumer expectations for quality lighting in the home,” says Jacques LE BERRE, director of marketing and business development, Lighting Solutions, NXP Semiconductors.