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Study Shows FD-SOI Most Cost-Effective Approach at 22nm

A new IC Knowledge report examines the costs of potential solutions for a foundry at 22nm.

What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than bulk.

We’ve known for a while that sticking with bulk at the 22nm node would get pretty complicated. This study shows just how complicated bulk will be: about 35% more process steps. That really adds up.

Some primary factors

Bulk

FD-SOI

Process steps

328

241

Wafer yield

97.70%

98.4%

Yielded wafer cost

$3,049.10

$3,013.60

Key results from IC Knowledge study of manufacturing costs at 22nm.

Real world scenarios

IC Knowledge has been doing these sorts of studies for over 10 years, so their Strategic Cost Models are tried and true.  In this case, they worked with Soitec and an independent wafer-processing consultant.

First, they determined the most likely scenarios for bulk and FD-SOI in terms of threshold voltages, gate oxides, stressors, metal layers and various design strategies. For the bulk model, they figured $130 for an epi wafer. For the FD-SOI wafers (they actually settled on two likely process strategies), they figured $500.

They applied the data to their model of a typical, well-run fab in Taiwan (they have to choose a place to accurately reflect things like labor and overhead), running 30K wafers/month at the 22nm node next year.

The Price is Right

The bottom line shows that whether you’re using standard bulk or FD-SOI, your per-finished-wafer cost is just a hair over $3000.

So for about the same price as bulk – or even less – you can get all the performance and power benefits of FD-SOI.

The IC Knowledge study doesn’t get into this side of things. But in case you missed it, FD-SOI does very well for both performance and power savings – at high and at low voltages. (See “FD-SOI: The Right Choice”.) At 0.7V, for example, FD-SOI is getting a +125% operating frequency improvement over bulk.  What’s more, if you’re on the design side, you don’t have to change your design flow, and you can re-use key IP.

The wafers are ready. The price is right. The results are fantastic. So what are you doing at 22nm?  Chances are it will be FD-SOI.

Note: the full FD-SOI cost report is available as a free download from IC Knowledge.

New Wii U™ on SOI

Nintendo’s next high-profile, high-volume CPU will leverage IBM’s 45nm SOI  for performance, power and eDRAM.

If you’ve followed the ASN “Buzz” in recent weeks, you’ve seen the news: the CPU for Nintendo’s upcoming (and very cool) Wii U is on 45nm SOI.

IBM’s been fabbing chips for Nintendo for over a decade, and first moved the company’s CPUs to SOI in 2006, at 90nm.  The Wii U, which got its debut at the recent E3 show, will hit the shelves in 2012.

While the new touch-screen remote gets a lot of attention, it is in fact the CPU in the box that does the heavy lifting.  The Wii U combines motion-sensing game play with full HD graphics. Players can use the new controller plus four more controllers simultaneously. The system is backward compatible for all games and accessories.

IBM says that the all-new, Power-based Wii U CPU will pack in some of its most advanced technology into an energy-saving silicon package.  The inherent advantages of SOI, explains the company’s press release, make it “a superior choice for performance-driven applications that demand exceptional, power-efficient processing capability – from entertainment consoles to supercomputers”.

Yes, Power-based Watson and the Wii U both use IBM’s small, stable and power-efficient on-chip embedded DRAM (eDRAM) on SOI, which is capable of feeding multi-core processors large chunks of data.  In the case of next-gen game consoles like the Wii U, that provides a smooth entertainment experience.

A few year ago, IBM first demonstrated the advantages – both in terms of technology and cost – of putting eDRAM on SOI.  Here at ASN, we were fortunate at the time to have IBM Fellow and eDRAM guru Subramanian S. Iyer explained the advantages of SOI.

As Dr. Iyer wrote in ASN in 2006, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs. […] We expect the use of eDRAM to proliferate to SOI in the 45nm generation.”

And here it is in the Wii U, right on target.

Cross section of IBM 45nm SOI eDRAM trench cell, circa 2006. The buried oxide is used to completely isolate the capacitor plate from the device. (Courtesy: IBM)

In a press release last fall, IBM said its “…embedded DRAM technology provides the most dense on-chip dynamic memory available today, enabling more than 1Gb of memory on a single chip. IBM eDRAM performance has advanced to a point where it can replace conventional on-chip static memory (SRAM) in many applications, taking up 60% less space on the chip, and consuming up to 90% less power.”

For the current Wii, IBM has shipped more than 90 million chips. The company’s looking for a repeat performance with the Wii U chips, which will also be produced at its 300mm fab in East Fishkill, N.Y.

Get Smart

ST’s latest BCD shows how SOI yet again enables huge reductions in power consumption.

What if you had to reduce power dissipation by 40x?

That’s exactly the task that fell to ST, under an EU program called Smart Power Management.

At the recent ISPSD (International Symposium on Power Semiconductor Devices and ICs) conference, STMicroelectronics and partners (GE Vingmed Ultrasound and Sintef) presented a paper on how they did it, using ST’s latest SOI-based Smart Power technology.

Paola Galbiati, ST’s Director of the BCD Technology Line, Technology R&D covered this project in her recent ASN article, “Smart Power Saves Power”.

As she notes, ST has been solving critical power management challenges with SOI-BCD (Bipolar-CMOS-DMOS) processes for almost a decade now. The technology they developed under the SmartPM project is a next-generation variation of their BCD smart power technology, combining SOI with 0.16-micron lithography.

While the technology is applicable to chargers for electric car batteries, the first proof point was done for ultrasound probes.

The trend toward 3D ultrasound using internal probes imposes draconian limits on power.  After all, you can’t have the doctor putting something hot and bulky down your throat in order to image your heart.

Transesophageal probes

Transesophageal probes,which are inserted into the esophagus via the throat, send a beam across the esophageal wall to image the heart structures. The constraints on space and power consumption for the embedded electronics are extremely stringent. (Courtesy: GE Vingmed Ultrasound AS)

2D probes typically have a couple hundred channels, consuming a total of about 3W of power.  But for advanced 3D imagery, thousands of channels are needed – with total power consumption cut to 1.8W:  about 40 times less.

This was not possible with  discrete components, but it is with technology like ST’s SOI-BCD, which enables chip designers to combine high-density logic circuitry (1.8V and 3.3V CMOS) with full dielectric isolation and a component portfolio. They can include power MOSFET transistors that can operate up to 300V, low noise devices and high-value resistors, leading to ASICs that couldn’t be implemented using conventional bulk-silicon substrates.

ST’s now got first silicon, so product design engineers can start planning a whole new generation of cutting edge solutions.

Add this to the fast-growing list of SOI-enabled game changers.

FD-SOI: The Right Choice

Although Intel will do FinFETs at 22nm, FD-SOI remains the better alternative for most all the industry for low power and mobile apps. In the weeks and months to come, we’ll continue hearing  the SOI camp addressing key points.

1. FD-SOI technology is the most cost-effective solution. The wafers are available from multiple sources. With volume purchasing, multiple mask layer savings and evolutionary design transition, FD-SOI comes in cheaper.

2. Ultra-thin SOI wafers are ramping in volume this year. Although for years, it was thought SOI wafers with super thin top silicon and BOX were beyond the purview of suppliers, Soitec has done it using their standard Smart Cut wafer manufacturing technology. These wafers are available now (see the ASN16 article where Soitec gives the details). Manufacturing lines are set to roll with industry ramp.

3. The ultra-thin SOI can include ultra-thin BOX. Much of FD-SOI will use ultra-thin BOX as well as ultra-thin top Si. ST is an example of a company doing great things here.  As they pointed out in a recent ASN article, “Designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.” The ultra-thin BOX and ground plane with or without bias enables this option with a simple process flow. Their hybrid co-integration approach on ultra-thin Si/BOX SOI lets them reuse bulk ESD and I/O IP.

4. FD-SOI does very well  for both performance and power savings – at high and at low voltages. The supply voltage (Vdd, which  essentially determines power consumption) is different depending on the app and the state of the device. Intel says its TriGate gets a 37% propagation time improvement (therefore enabling improvement of operating frequency by 58%) over the previous generation at 0.7V; but FD-SOI is getting a +125% operating frequency improvement. The SOI Consortium recently published data about FD-SOI on an ARM chip.  Now they’re working on further data, and on lining up the ecosystem.

For the real world of high-performance, low-power mobile apps, planar FD-SOI really looks like the way forward.  For those in the fabless world, it gives game-changing results without changing existing design flows or manufacturing processes. The SOI Consortium has a terrific Q&A if you need more about planar-FD-SOI in general.

Intel does amazing things on the fab floor, to be sure. But the FD-SOI camp has done the math, too – and they’ve got a very different story to tell. Watch this space!

GPU/CPU on SOI: the Xbox 360 did it first

Microsoft and IBM moved the CPU and the GPU of the best-selling game console in North America onto a single SoC – a year ahead of the pack.

There’s a lot of excitement about the “latest trend” of integrating both the computing chip – the CPU and the graphics chip – the GPU – into a single chip. But in fact, the first GPU/CPU system-on-chip (SoC) came out in June 2010. It’s on 45nm SOI, is produced by multiple foundries, and is at the heart of the hottest selling game console in North America: the Xbox 360.

 

Xbox 360 GPU/CPU SoC Chip Statistics:
• 372M transistors
• 45nm SOI, Ultra-low k dielectric
• 10 levels of metal
• 153 array types, ~1000 instances
• 1.8 million flip flops
• 6 PLLs
• 12 clock domains
• Compared to 2005 CPU GPU:
• >60% Power Reduction
• >50% Silicon Area Reduction
(Courtesy: IBM & Microsoft)

The technical community refers to it as the Xbox 360 S – “S” for “slim”, because the new chip enabled a host of slimming effects. The two most important were a slimmed-down power budget (43% less than the previous generation) and a serious reduction in the bill-of-materials (always good news for the bottom line).

Power down

You might think that the GPU/CPU combo also provided a major performance boost. But in fact, for game console lifetimes, one thing you can’t do is toy much with performance. Game developers count on having a stable platform – they need it to work just the way they first planned it for the entire console life cycle.

One of the advantages SOI gives to chip designers is that it’s a powerful “knob to turn” – they can ratchet up performance (and keep about the same some power budget), or drastically reduce power (in exchange for a less dramatic performance increase), or they can find a balance somewhere in between.

In the case of the Xbox 360 GPU/CPU, one can surmise that since they couldn’t boost performance too much, they had the luxury of turning the knob way down for power. And that translates into a whole lot of benefits.

But first let’s look at what they actually did.

2 for 1

The first Xbox 360 came out in 2005, with a CPU on 90nm SOI (see ASN #6) and a GPU on 90nm bulk. A few years later, the chips were migrated to 65nm. Then in 2010, the two were combined on a single chip using 45nm SOI.

For the IBM and Microsoft chip design team, the latest challenge involved both a port (the bulk GPU to SOI), a shrink (to 45nm) and a complete redesign of the GPU (which had originally been designed by ATI). However, from a graphics standpoint, the resulting chip had to remain functionally identical to the old GPU, to ensure the backward compatibility of the games.

It also involved removing the front-side bus (FSB), which handles functional intercommunication between the CPU and GPU blocks.

The Xbox 360 CPU and GPU process migration history. (Courtesy: IBM and Microsoft)

Compared to having two chips, putting the two units into one chip saved 60% in power and 50% in area compared to the 90nm versions.

Savings abound

In terms of silicon, the savings are obvious when you’re fabbing one chip instead of two. However, the ramifications for savings extend far beyond the silicon.

Consider thermal design, for example. Instead of cooling two chips, you just have one: so one heatsink; one fan. And with good thermal management, the fan speed is lower – so it’s significantly quieter and needs less power for the fan.

 

Left: The final 35mm x 35mm package includes the integrated GPU/CPU and an eDRAM. (Courtesy: IBM & Microsoft)
Right: The GPU/CPU SoC simplified the motherboard layout. (Courtesy: Microsoft & IBM)

This simplifies the motherboard layout and power delivery. And of course, between the lower power chip and the slower fan speeds, they could use a smaller power supply unit.

All these factors combined to enable a reduction in console size. However, the new chip is robust enough to also seamlessly handle the high-performance processing for Microsoft’s Kinect – the new motion sensor that replaces the controller.

 

The new Xbox 360 GPU/CPU also handles the processing for the Kinect motion sensor. (Courtesy: Microsoft)

In January 2011, Microsoft announced that the new Xbox 360 had just capped off six consecutive months as the best-selling console in North America. More than 50 million Xbox 360 consoles have been sold worldwide – double the amount of the previous generation Xbox.

Sales are up 27% year on year, and Microsoft has indicated that this console should keep going strong through 2015. Which shows that great things happen – and keep happening – on SOI.

A special thanks to Bob Drehmel of IBM for his technical guidance on this article.

MEMS on SOI – Growing Fast and Faster

In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions.

MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate.

The first application of the tiny SOI-MEMS Nanopump™ will be for treating diabetes. (Courtesy: Debiotech)

One of my favorites is Debiotech’s tiny insulin NanopumpTM targeting diabetes, fabbed by ST.  As Debiotech’s Laurent-Dominique Piveteau noted, “…the use of SOI wafers for fabricating the Nanopump MEMS device has significant medical and economic advantages.  The SOI-based structure allows for the highest reliability in the smallest possible package, enabling very tight control and precision of the pumping mechanism. The flow rate is steady, and it is insensitive to pressure, temperature, viscosity and aging. It also offers extreme dosing precision.”

Reasons cited by other contributors for using SOI  for MEMS include:

  • Eliminating the stress problems common in polysilicon;
  • Ensuring well-defined film thickness for more accurate oscillation frequency of moving parts;
  • Providing greater surface and sidewall smoothness;
  • Enabling thinner structures;
  • Increasing thermal conductivity of MEMS components.

But the bottom line is that it’s the most cost-effective solution for their state-of-the-art MEMS devices.

MEMS also figure in two of the most recent ASN Buzz postings:

VTI’s SOI-MEMS multi-axis accelerometer is the “stride sensor chip” in the miCoach real-time training system (Courtesy: VTI Technologies, adidas and Samsung)

In the next few weeks, we’ll also be posting a new article by Soitec on their Smart Stacking(tm) technology for the next generation of MEMS with pre-etched cavities, among other things.

If you’d like to see more of the why’s and wherefore’s of SOI-MEMS apps, just type “MEMS” into ASN’s search engine.  You’ll get dozens of pieces from and about leaders like ST, ADI, Denso, VTI, Tronics, IBM and more.

It’s a pretty fragmented world, still, so if you know cool SOI-MEMS apps we should be covering, would you let me know?

The SOI Papers at ISSCC 2011

The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront.

As always, performance gains generate plenty of buzz. But the SOI papers were also notable for work reducing power consumption, extending scalability and overcoming threshold voltage variation.

IBM presented the world’s highest frequency microprocessor to date, clocking in at 5.2 GHz. On 45nm SOI, it’s the first commercial processor ever to break through the 5GHz speed barrier, and is the centerpiece of Big Blue’s new zEnterprise 196 system.

In another paper, IBM presented the first embedded high-k/metal-gate (HK/MG) SRAM on 32nm SOI enabling operation at down to 0.7V.

AMD presented its Bulldozer 2-core modules, which are on 32nm SOI with HK/MG. Clocking in at 3.5GHz, we’ll see them beginning in desktop and server Fusion chips this year.

In a quieter but clearly significant paper, ST and Leti compared 65nm low power (LP) partially depleted (PD) SOI with standard 65nm LP CMOS bulk. They found that PD-SOI, when combined with a low resistivity produced with forward body bias of the power switch, can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.

For summaries of additional SOI-based papers at ISSCC and other recent conferences, see ASN’s PaperLinks.

SOI Consortium’s phenomenal FD-SOI/ARM results

Up to 80% additional performance improvement on an ARM Cortex M0. 40% lower power for SRAMs. These are the amazing planar FD-SOI results just announced by the SOI Consortium.  Things are suddenly looking much brighter in the world of low-power, high-performance chips for mobile and consumer apps.

An A-list of companies collaborated on this assessment/characterization – ARM, GlobalFoundries, IBM, ST, Soitec and Leti – so you know the results are really solid.  People want PC performance in a cell phone (without having to recharge the battery three times a day, thank you!). These guys know what it takes to make the chips that can make it happen.

For designers and manufacturers, FD-SOI is a win-win:  design flow is the same as bulk, so there’s no learning curve; manufacturing is vastly simplified, so it costs less.

Let’s make a few things clear here:  that +80% – that’s on top of the +25% improvement you’d get moving from one node to the next.  So if you move to FD-SOI at the same time you’re moving down a node, you can get (do the math) a +125% (!!) improvement in performance – and lower power. Designers sweat blood for a few percentage points of performance improvement, and here you get more than double – and it’s cheaper and easier. Wow.

The 40% power savings on the SRAM (which now typically accounts for over half the chip) – that’s because with FD-SOI you can run it reliably at lower voltages – which of course saves battery life.

It’s worth pointing out that much of this success is due to some amazing work by Soitec.  Their R&D folks first wrote about the ultra-thin wafers needed for FD-SOI in ASN five years ago.  They’ve been working on perfecting those wafers ever since – and supplying them to the IDMs and foundries for some time now, so those guys could get on with their early legwork.  The requirements for silicon and BOX layer thinness and smoothness are draconian:  we’re deep in the world of Angstroms here.

All the while, there were some hefty naysayers claiming the wafer requirements could never be met.  But guess what: those requirements have been met – and the wafers are ready to roll.

I urge you to read Christophe Maleville’s article in our most recent edition: Wafers for Fully-Depleted Devices: Ready for Volume – and look at the all the checkmarks on that list of requirements. It’s really some impressive work.

So, want to know more FD-SOI? Let me point you at some sources:

Planar FD-SOI: it’s the start of something big.

AMD’s New Fusion APU’s on 32nm SOI

The AMD PR folks are calling their new Fusion APUs the era of  “Personal Supercomputing”  – and its flagships are on 32nm SOI   We’ve been hearing about these revolutionary chips for years now – the “Fusion” of graphics chips – GPUs – and CPUs on a single piece of silicon, which they’re referring to as an APU – an “Accelerated Processing Unit”.

Launched last week at CES in Las Vegas, the SOI-based “mainstream platform” is primarily intended for performance and mainstream notebooks and mainstream desktops. First up is the 32nm die A-Series “Llano” APU, which includes up to four x86 cores and a DirectX 11-capable discrete-level GPU.  It’s scheduled to ship in the first half of 2011 and appear in products mid-year.

Now, with a bit of detective work, we can sort out the SOI-based APU roadmap that AMD announced at its Financial Analyst’s Day in November 2010.

AMD divides its roadmap into “Notebooks”, “Desktop” and “Server”. Here’s what to look for on 32nm SOI.

Notebooks – CPU/APU Roadmap:

  • “Llano” Fusion APU – has 2-4 “Stars” CPU cores  – comes out this year (the 45 to 32nm SOI port of “Stars”, which is based on the existing architecture, was detailed at ISSCC last year)
  • Next year (2012), they’ll add the “Trinity” Fusion APU, based on 2-4 all-new next-gen “Bulldozer” CPU cores

Desktop CPU/APU Roadmap:

  • This year, look for the “Zambezi” CPU, with 4-8 Bulldozer CPU cores
  • and the “Llano” Fusion APU with 2-4 Stars CPU cores
  • Next year, it’s the “Komodo” CPU with 8 Bulldozer CPU cores,
  • and the “Trinity” Fusion APU with 2-4 next-gen Bulldozer cores

Server CPU Roadmap:

  • This year, it’s the “Interlagos” CPU with 8/12/16 Bulldozer CPU cores
  • and the “Valencia” CPU with 6/8 Bulldozer CPU cores
  • Then next year, it’s the “Terramar” CPU with up to 20 (!!) next-gen Bulldozer CPU cores,
  • and “Sepang” with up to 10 next-gen Bulldozer CPU cores.

GlobalFoundries is of course the fab – debuting 32nm SOI with high-k/metal-gate (HK/MG).  Here’s what CEO Doug Grose showed financial analyst’s at the end of 2009 (yes, so you can tell any doubters that GloFo was already showing great HK/MG 32nm SOI over a year ago!):

And here’s what Chekib Akrout, senior vice president and general manager, AMD Technology Development, showed the financial analysts in November 2010:

Very cool stuff.  What do you think?  Will it find its way into your products or onto your desktop this year?

Then of course there’s all these changes in the upper echelons of AMD management that transpired this week, plus the Intel/nVidia settlement.  What does your crystal ball say about all that? Leave a comment and let us know.

(All images courtesy of AMD.)

2011 & SOI: Doing It.

What will 2011 bring in the world of SOI? The hot topic will no doubt be FD-SOI – the planar, fully-depleted SOI solution that’s the top contender for mobile, low power and SoC apps at the 22nm node. You’ll be learning about how it will maximize performance, manufacturability and reduce overall cost. The pieces are all in place – the wafers, transistor designs and models are ready to roll – and from a design perspective, it’s pretty much transparent.

On the more immediate front, my personal crystal ball reveals great inroads into ever-broader areas. As always there’s exciting activity in high-performance systems, gaming consoles and the like, but there’s a lot more beyond that, too.

Embedded markets – the need for higher performance and lower power is answered with things like expanded foundry offerings from IBM, growing support from the ARM community, and high-volume chip production from leaders like Freescale and NXP. Great opps for apps in high-temp, automotives, imaging & RF, too.

Lighting – NXP’s solutions for major improvements in compact fluorescents (CFLs) will raise the bar for the designers in the massive lighting industry.

Power management – at the intersection of analog and digital, traction is growing in this quiet but significant corner of the embedded world, lead by Infineon, NXP, ST, IBM and more.

MEMSST’s airbag sensors and Debiotech’s insulin delivery systems are examples of the sorts of very cool, leading-edge apps now heading out into the real world.

On the design front, the message that SOI is evolutive, transparent, and cost-effective (not elitist, complex and expensive) will gain momentum in the greater design community. With the opportunities that SOI brings for lowering power and boosting performance, 2011 is the year the fabless folks really start to do it.

In the current issue of ASN (#16), VLSI President Risto Puhakka sees good growth this year, with critical mass hitting at the 32nm transition.

What do you see? How will you be using SOI this year? What about FD-SOI at 22nm? Leave us a comment and let us know.