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SOITEC and UCL boost the RF performance of SOI substrates

Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of wireless communication standards.

In 2003, UCL demonstrated the possibility of further improving the RF performance of HR-SOI substrates by minimizing or even eliminating the so-called parasitic surface conduction inherent in any oxidized silicon substrate [1]. UCL proposed a figure of merit, the effective resistivity, which helps compare the RF performance of various technological solutions as well as monitoring in-line the quality of fabricated substrates.

The effective resistivity accounts for the wafer inhomogeneities (i.e., oxide covering and space charge effects) and corresponds to the resistivity that a uniform (without oxide nor space charge effects) silicon wafer should have in order to sustain identical RF substrate losses. In other words, it is the value of the substrate resistivity that is actually seen by the coplanar devices.

Therefore, comparing the wafers in terms of their effective resistivity allows us to isolate the performance of the substrate by eliminating series losses and skin effect inside conductors. The interest of the effective resistivity as a factor of merit is not limited to the monitoring of the RF quality of the fabricated substrate but it is also a physical parameter which is used by RF designers to properly model the impact of the substrate.

A new substrate is born

Soitec and UCL have been working together to identify the technological opportunities to still further improve the high-frequency performance of commercially available HR-SOI substrates. Thanks to the introduction of an engineering substrate handle, Soitec can now provide a new flavor of HR-SOI called eSI, for enhanced Signal Integrity (see Figure 1) substrate (previously named Trap Rich) with a measured effective resistivity as high as 10 [2].

New generation of HR-SOI substrate

Figure 1. A new generation of HR-SOI substrate: enhanced Signal Integrity (eSI) (Image courtesy of Soitec)

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along CPW lines and purely capacitive crosstalk similarly to quartz substrate. It has been demonstrated that the presence of a trap-rich layer does not alter the DC or RF behavior of SOI MOS transistors [3].

Besides the insertion loss issue along interconnection lines, the generation of harmonics in the Si-based substrates has been investigated. HR-SOI substrate presents reduced harmonics compared with standard SOI substrate and the introduction of engineering eSI substrate handle leads to harmonics levels well below the wireless communication systems [4] (see Figure 2).

Harmonic distortion along a 2,146 µm-long CPW line

Figure 2. Harmonic distortion along a 2,146 µm-long CPW line when a signal at 900 MHz is injected at the input for a trap-rich HR-SOI wafer from SOITEC. The specification (specs straight line) for the harmonic distortion corresponds to that of RF switches for GSM/EDGE transmitter modules [5].

The improvement of the HR-SOI substrate brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors, for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc.

Thanks to the introduction of eSIengineered substrate handle, the HR-SOI substrate can really be considered as a lossless Si-based substrate. eSI HR-SOI technology opens the path to further system integration in the Front End Module space as well as even more complex mixed-signal System-on-Chip (SoC).



A BIT OF HISTORYFor over 15 years, UCL’s Raskin research group has been developing high-frequency characterization techniques, which are today widely used by industry as well as other research teams. The group has been measuring advanced MOS devices (fully and partially depleted SOI transistors, FinFETs, Ultra-Thin Body and BOX (UTBB) devices, silicon nanowires, Junctionless multiple gate MOSFETs, etc.) from international research centers and companies.

UCL's Welcome platform

Figure 3. UCL’s Welcome platform: electrical characterization room of 350 m2.

The experimental platform known as “Welcome” at UCL (see video) is equipped with the latest electrical measurement equipment covering on-wafer measurements over a wide frequency range (DC up to 110 GHz) and temperature range (4K up to 300°C). UCL also has 1,000 m² in cleanroom facilities, including an SOI CMOS process (see Figure 4).

UCL's Winfab

Figure 4. UCL’s Winfab has 1000 m² of class M1 cleanroom facilities

In 1997, Prof. J.-P. Raskin presented pioneering work on the RF performance of HR-SOI substrates [6]. This paper demonstrated the great interest of HR-SOI substrates to reduce RF losses as well as the crosstalk in Si-based substrates.

In 2005, the team demonstrated the possibility creating HR-SOI substrates characterized with an effective resistivity as high as 10 thanks to the introduction of a high density of traps at the BOX/HR-Si handle substrate [3]. Those traps originated from the grain boundaries in a thin (300 nm-thick) layer.

In 2011, with former PhD student Dr. Mostafa Emam, the team launched a spin-off company, Incize (, which offers RF electrical characterization services.


[1]    D. Lederer, F. Brunier, C. Desrumaux and J.-P. Raskin, “High Resistivity SOI substrates: how high should we go?”, IEEE International SOI Conference, Newport Beach Marriott Newport Beach, CA, USA, September 29 – October 2, 2003, pp. 50-51.

[2]    K. Ben Ali, C. Roda Neve, A. Gharsallah and J.-P. Raskin, “RF SOI CMOS technology on commercial trap-rich high-resistivity SOI wafer”, IEEE International SOI Conference – SOI’12, Napa, CA, USA, October 1-4, 2012, pp. 112-113.

[3]    D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity”, IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, November 2005.

[4]    C. Roda Neve and J.-P. Raskin, “RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 924-932, April 2012.

[5]    M. Carroll et al., “High-Resistivity SOI CMOS Cellular Antenna Switches,” CSIC 2009, October 2009, Greensboro, NC, pp. 1-4.

[6]    J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk reduction using SOI technology”, IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252-2261, December 1997.

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (

Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing

For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS processing to deliver high-performance, high-volume RF devices that meet the cost and performance goals of the most competitive markets. The development of UltraCMOS being a laboratory curiosity, to becoming the RF Front End (RFFE) process of choice, has included two decades of process development, breakthrough innovations and key inventions.

Highly Insulating Substrate

The use of sapphire as a highly insulating substrate for RF Silicon-on-Insulator (RF SOI) CMOS processing began when visionaries took advantage of sapphire’s exceptional properties and overcame the limitations that previous researchers had encountered. The properties of synthetic sapphire, or aluminum dioxide (alumina), include 1014 ohm/cm resistivity, making it a near-perfect insulator. Additionally, sapphire has good thermal properties. These combined attributes make sapphire well suited for use as a semiconductor substrate.

As shown in Figure 1, Peregrine Semiconductor’s UltraCMOS technology involves combining silicon with the highly-insulating substrate without incurring major defects, resulting in a highly-manufacturable semiconductor process. This process can be implemented in any standard CMOS foundry, leveraging existing CMOS capacity and avoiding substantial investment, while maintaining technology leadership.

UltraCMOS process

Figure 1. The UltraCMOS process, an advanced HR-RFSOI technology, can be implemented in any standard CMOS foundry.

UltraCMOS technology was first used for Phase-Locked Loop (PLL) products designed for the infrastructure market, as well as space applications that relied on the inherent radiation tolerant (rad-hard) performance of sapphire, as well as the latch-up and Single Event Upset (SEU) immune UltraCMOS process.

progressive improvement in RonCoff

Figure 2. The progressive improvement in RonCoff established by the STeP2 process technology is maintained, today.

The key to developing the platform that has provided a more than 20% year-over-year (YOY) performance improvement is attributed to adapting Moore’s Law, plus internal knowledge of device physics. As opposed to simple scaling, significantly improving the basic Field Effect Transistor (FET) performance is achieved by reducing the on resistance of the channel, or improving the breakdown voltage, or the linearity, of the device. One performance metric for the FET is based on the product of the resistance from the “on” state and capacitance from the “off” state that provides a Figure of Merit (FOM) for the process technology, called “RonCoff.” For UltraCMOS-based products, an improvement in RonCoff relates directly to the improvement of the device performance and size reduction.

For Peregrine, high-volume production began with RF switch products based upon its Semiconductor Technology Platform 2 (STeP2). As shown in Figure 2, from the 0.5-µm STeP2 process in 2004 to STeP5 in 2012, Peregrine has been able to maintain a 20% YOY improvement in RonCoff. The combination of the process, device, and modeling capabilities that allow fabrication in any standard CMOS facility has proven to be a successful, sustainable strategy for RF performance, enabling fast-track RFFE performance and an accelerated roadmap.

Semiconductor Technology Platform (STeP) 8: A Major Step Forward

Continuing down the process roadmap shown in Figure 2, 0.25 µm, bonded(1) STeP8 technology provides the largest improvement in RonCoff performance for a 12-month window. Instead of obtaining a 20% YOY reduction, the development team’s efforts achieved a 36% YOY decrease within one year of the announcement of the previous generation of STeP technology, STeP5. In addition to greatly exceeding expected performance targets after ten years of process of development, this demonstrates that the STeP roadmap is sustainable for even further improvements. With STeP8 process technology at 250 nm, there is a long runway led by digital technologies that are now at 22 nm.


The industry and 3GPP standards body specified the input third order intercept point (IP3) as the required degree of linearity, which helps to avoid interference with other devices on the network. The modelers, process engineers and designers at Peregrine determined where the nonlinearities were occurring and invented HaRP™ technology to significantly improve the harmonic performance of their products. This device-level technique increases the IP3 linearity and improves the switch linearity of UltraCMOS products by more than 10 dB (an order of magnitude), on average. Figure 3 illustrates the performance improvements that HaRP technology enhancements enable.

HaRP™ technology-enabled prototype RF switch versus a switch without HaRP technology enhancements

Figure 3. The first HaRP™ technology-enabled prototype RF switch versus a switch without HaRP technology enhancements demonstrate the technology’s ability to achieve 3rd harmonic phase requirements at 5:1 VSWR (conditions: 3fo, Tx1, 33.5 dBm, 2.6V, 915 MHz).

The HaRP invention established Peregrine as a leading provider of high-performance RF switches in the market. Since the technology is applied to GSM/WCDMA switches, this rapidly led to very high-volume production. Peregrine applied the implementation of the device-level technology into its entire RF product portfolio, beyond switches. This capability led to an accelerated STeP process roadmap designed to optimize and advance HaRP technology performance.

UltraCMOS® STeP capabilities

Figure 4. UltraCMOS® STeP capabilities meet the ever-increasing IIP3 linearity requirements of 2G, 3G, and 4G networks.

According to the Shannon limit (the theoretical maximum information transfer rate of the channel), the more linear the components are, the higher the data rates that can be achieved in the communication channel. As shown in Figure 4, STeP8 has demonstrated input IP3 (IIP3) performance that exceeds 77 dBm.  With the communication industry’s demand for improved linearity, the ability of STeP2 to meet/exceed 2G requirements of 55 dBm, STeP3 to meet 3G requirements of 65 dBm, STeP5 to exceed 4G LTE 72 dBm requirements, and STeP8 to provide even greater performance allows continued progress in this critical area.

STePs to Higher RF Performance

Peregrine has demonstrated a path for advancing UltraCMOS STeP technology to meet market requirements. To meet the industry’s projected 78% compound annual growth rate (CAGR) from 2011 to 2016, expanded network capacity is expected to come from improved radio link performance, Multiple Input/Multiple Output (MIMO), Carrier Aggregation (CA), new infrastructure, and new spectrum. Peregrine Semiconductor expects to deliver UltraCMOS RFFE products to meet all of these requirements. STeP10 devices are currently in laboratory evaluation and the results look promising to follow this path, with no foreseen limits to advancing the technology further.

(1) bonded silicon on sapphire (BSoS) substrates from Soitec

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

logos_blueIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
Hyatt Regency Monterey Hotel and Spa, Monterey, California
October 7th thru 10th, 2013

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS technology: The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. An additional third track on 3D Integration is also being included, which will emphasize invited talks from world-renowned experts in 3D technology as well as contributed talks from leading research groups and industry.

So all-in-all, attendees can access essentially three conferences with one registration fee, covering three topics at the heart of today’s industry plans:

  • Silicon on Insulator (SOI) – Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-on-Insulator technology, including CMOS, photonics, sensors, NEMS and more. The conference will cover topics spanning from material engineering to circuits and applications, through devices and modeling. There is no better place than this conference to understand the underlying physics of FinFET as fully-depleted devices have always been an important topic.
  • 3D Integration – 3D Integration allows us to scale integrated circuits “orthogonally” in addition to classical 2D device and interconnect scaling. A dedicated session will address the unique features of such stacking with special emphasis on wafer-level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques and bonding methods, as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed.
  • Subthreshold Microelectronics – Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low-power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics.

Conference format

This year, the conference will run two parallel sessions for SOI and Subthreshold Microelectronics. A joint technical session dedicated to 3D integration will also be hosted in addition to the parallel sessions.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

The rump session will lead to lively discussions about the next big changes that will occur in CMOS devices.

Of course, the social events will be maintained as usual. The welcome reception, banquet dinner and cookout are excellent opportunities for people from different backgrounds to meet in a friendly atmosphere, especially this year. There will be specialists from the different fields described above, representatives from established industries as well as startups, professors and scientists from universities and research institutes all over the world. This will be a perfect mix to generate new ideas, start collaborations and initiate new projects.

Optional classes

On top of the regular sessions, this year the conference will offer attendees the possibility to follow one of two different short courses as well as one of two different fundamentals classes.

One short course will focus on 14nm Node Design Methodology (both bulk and SOI, FinFET and planar) and the 3D short course will cover the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects in 3D silicon and packaging.

The SOI fundamentals class will discuss the post-silicon era, including device and material aspects.

The Sub-Vt fundamentals class will cover design techniques for robust sub-Vt operation of integrated circuits. Two key areas will be covered by experts in their fields. First, Professor Massimo Alioto (U. di Sienna, Intel Labs) will instruct attendees on sub-threshold VLSI digital circuits and systems, from microprocessors to memories. Second, Professor Peter Kinget (Columbia U.) will review the challenges for ultra-low-voltage analog and RF circuits and discuss design opportunities to circumvent them. This class is fundamental for anyone considering low-voltage and sub-Vt operation in circuit design.


This year, the conference will take place in the splendid Hyatt Regency Monterey Hotel and Spa, located in Monterey, CA, a beautiful waterfront community on the central coast of California.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

This area offers breathtaking scenery and a profusion of indoor and outdoor activities.

Important dates

Paper submission deadline: 31 May, 2013
Notification of acceptance: 30 June, 2013
Short course date: 7 October, 2013
Conference date: 7 – 10 October, 2013

More details are available on the S3S website.

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, reliability, and product performance.

Bulk vs. SOI basics

In bulk wafers, isolation is formed in a manner similar to planar devices, with implanted wells and shallow-trench-isolation oxide separating fins from one another.

With an SOI (silicon-on-insulator) wafer, however, the fins are formed in the silicon layer, the isolating dielectric is already extant, and no well implants are required.

Schematic representation of bulk junction and Fig1: dielectric-isolated FinFETs

Figure 1: Schematic representation of bulk junction and dielectric-isolated FinFETs

The most important differences in the devices formed in these two manifestations lie in the shape of the fin, the processes that determine the effective fin height, and the presence of doping, which consequently affects the device in many adverse ways such as the variability and the reliability.

The final realization of the full potential of fully-depleted FinFETs is dependent on optimally addressing the issues enumerated herein. Dielectric isolation is shown to provide superior characteristics in all of the above-named aspects. Figure 1 shows a schematic representation of FinFETs for the two isolation architectures, with the various critical points of distinction noted as are discussed below.

Fin Shape

Definition of the fins on an SOI wafer is relatively straightforward; vertical fin sidewalls may easily be obtained.

Fig2: Typical bulk junction and dielectric-isolated FinFET fin profiles

Figure 2: Typical bulk junction and dielectric-isolated FinFET fin profiles

In a bulk-based process, as the spaces between the lower, electrically inactive portions of the fins must be filled with an insulator, some angling of the fin is required to prevent the formation of voids.

Bulk and SOI fin profiles are pictured in Figure 2.  As tapering the fin compromises the subthreshold slope and degrades the effective drive current as well as the output conductance, minimization of the taper is important to the electrical integrity of the device.

Bulk: Doping in the Fin

Whereas in an SOI design the transistor-transistor and subfin source-drain current paths are inherently interrupted by the dielectric layer, in a bulk-based process adequate doping for electrical isolation and latchup immunity needs to be established.  This requires additional masking levels and connections for electrical bias.

Conventional design criteria of doping, depth, and overlay tolerances apply to the deep interdevice isolation wells, but suppression of undesired current in the drain-source region has unique features in the FinFET configuration.

Suppression of punchthrough current requires some level of doping at least in the bottom portion of the fin. The adverse effects of doping on mobility and random-dopant-fluctuation have been reported; non-uniform doping is particularly egregious as it increases capacitance without a concomitant increase in drive current.

However, the level of doping required depends on the alignment of the gate and the source junction depth. An optimum choice for the conjunction seeks to minimize the dopant required while respecting physical process window constraints (see Figure 3).

Fig3: Short-channel effects

Figure 3: Short-channel effects as a function of doping and gate recess depth relative to the source junction depth in bulk FinFETs

Another adverse effect of doping in the fin is the implication for the gate work function. For junction-isolated FinFETs, the gate metal work function is established so as to provide the desired threshold voltage in the presence of doping; for undoped dielectric-isolated FinFETs the appropriate work function is closer to midgap, which reduces gate leakage and improves reliability.

Fig4:  Voltage operating range as a function of fin doping

Figure 4: Voltage operating range as a function of fin doping

Between RDF-driven Vmin and work function-driven Vmax, the operating window of bulk FinFETs is more limited than that of undoped SOI FinFETs (see Figure 4).

Product and Circuit Design Considerations

Designing with planar bulk technology has historically differed from planar SOI technology in three aspects: well contacts, self-heating, and floating body effects.

At the expense of area, planar bulk technology has enjoyed the advantages of controlling the threshold voltage through the well potential.  No such benefit exists in bulk FinFET devices, as it is not possible to influence the transistor through the well bias except in the spurious and undesirable region below the active fin.

In fully-depleted devices the concept of a floating body (charge storage in an isolated neutral region) is not applicable, so SOI and bulk FinFETs behave the same way for all switching scenarios.

Self-heating effects, while not important for fast switching operation, can be relevant for DC circuits. While large-area planar structures will continue enjoy the advantage in thermal conduction relative to SOI traditionally observed, bulk and SOI FinFETs have very similar self-heating characteristics, as the only difference in thermal conductance is a tall, thin sliver of silicon, which provides only a small increase in thermal conductance.

While bulk FinFET technology has lower soft error rates than planar bulk technology, SOI FinFETs are better yet.


Fin height variation has a much more serious impact than the planar analog of transistor width variation. Wide transistors (i.e., many fins) have the same variation as narrow (i.e., few fins).

Fig5: Calculated dependence of SOI and bulk transistors

Figure 5: Calculated dependence of SOI and bulk transistors on key process variations, and relative variations in the two architectures

Whereas in the SOI-based version the electrical fin height is determined by the starting silicon thickness, in the bulk-based FinFET process the fin height is determined by several processes, and the distinction between “active” and “inactive” fin is blurred by the conjunction of the gate alignment with the source junction.

The sensitivities to various key variables have been calculated with hardware-calibrated 3D simulations, and the variation of those key parameters determined with respect to state-of-the-art processes (see Figure 5).

The fin variation-driven performance tolerance of a bulk FinFET is larger than that of an SOI FinFET.   That benefit of SOI is not only found in sort yield and worst-case design corners, but smaller variation within a chip enables a faster chip for any given level of leakage.


Complete realization of the benefits of fully-depleted transistor architecture is affected by the choice of isolation. Increased range of operating voltage, process simplification, reduced variation, lower soft error rate, and higher circuit density are all features of a dielectric-isolated architecture.

For these reasons the ability of an SOI-based FinFET to reap the full benefits of fully depleted transistors is demonstrably superior to a doped, bulk-based implementation.

The Transition to Fully Depleted

The SOI Industry Consortium is actively engaged in supporting the industry’s transition to fully-depleted (FD) technologies.

FD technologies offer:

  • better electrostatics, so you’ve got stronger gate control;
  • and lower channel doping, which enables better SRAMs that can operate stably at lower supply voltages – resulting in power savings of up to 40%.

There are two main flavors of FD technologies:

  • planar (aka “2D” or FD-SOI), which leverage ultra-thin SOI wafers;
  • vertical (aka “3D” or FinFET), which can be built on bulk or SOI wafers

Here are some of the main points we’re making.

FD Planar Closes the Gap

Planar FD transistors are cost effective and help close the FinFET gap while maintaining the design infrastructure.

They offer:

  • >30% advantage in performance in logic devices at 20nm (compared to planar bulk)
  • 40% reduction in power
  • over 50% reduction in power in memory (SRAM)
  • cheaper/better isolation
  • cheaper device integration
  • improved SER
  • better electrostatics
  • better low voltage operation
  • potential for back gate control
  • improved Vmin
  • no floating body issues

Planar FD significantly simplifies the manufacturing process, resulting in impressive per-die savings as compared to bulk – a point which is now garnering attention.

The value proposition is there: power, performance, cost and variability control. And perhaps most importantly, it’s available at 28nm to the fabless community now, through  Consortium members STMicroelectronics and GlobalFoundries.

Fins on Oxide Are Superior

With oxide-isolated fins, the isolation process is simpler and less expensive. Many of the control issues are improved over bulk isolated FinFETs. The result is faster time-to-market and better power/performance.

With respect to variability control, starting on an SOI substrate enables:

  • lower doping in Fins
  • reduced (RDF) Variability
  • lower Vmin; better analog
  • superior Fin-height, Fin-width, taper, Control

In terms of process, starting on an SOI wafer as opposed to bulk means:

  • no STI, no well implants
  • reduced time-to-market
  • greatly simplified fin etch, shape and control
  • reduced fab cycle time

With SOI, dielectric isolation is superior. This results in:

  • no sub-fin leakage path
  • immunity from long-range parasitic conduction
  • high-temperature operation integrity
  • significantly better SER
  • latch-up immunity

So when considering the bottom line, FinFET on insulator (compared to FinFET on bulk) is:

  • 5 to 7 quarters faster
  • less expensive
  • better performance
  • area savings
  • supply current (Iddq) 30% lower
  • minimum operating voltage (Vmin) 50mV lower

The Substrate Supply Chain is in place

There are at least 3 major substrate vendors supporting the transition to fully-depleted technologies. Their combined output will easily provide the required industry volume, and can be expanded if needed.

IDC predicts that worldwide smartphone shipments will reach over 1.16 billion in 2016. The processors will require about 1.3 million wafers/year. (See figure.) The combined capacity of the existing suppliers is 2.3-2.4 million wafers/year by early 2014. They have indicated that additional factory capacity can be put in place within a 12 month window, so incremental capacity can quickly reach 3 million wafers/year – more than enough to meet projected demand.

At the SOI Industry Consortium, we are extremely pleased with the traction we’re getting. With the first FD-SOI products hitting the shelves, we think 2013 will be an exciting year.

Worldwide smartphone shipments

Worldwide Smartphone shipments from 2010 to 2016 (in million units)
> The combined capacity of the existing suppliers is 2.3-2.4 million wafers/year by 2014 (early)
> Additional factory capacity can be put in place by the substrate suppliers : within a 12 month notification, incremental capacity of 3 million wafers/year
(Source: IDC)

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, and can compromise power, performance, and manufacturability.

Here we briefly explore several important aspects regarding the benefits of employing Fin-on-Oxide (FOx) isolation of the active FinFET channel region from the substrate semiconductor over that of first-generation bulk FinFETs, and examine how FOx as enabled on an silicon-on-insulator (SOI) wafer is well-positioned to deliver optimal FinFET value in 2nd Generation CMOS technology.

Isolation-Related Manufacturing Challenges

In a bulk a FinFET process, fins are formed in bulk silicon, an isolation oxide (SiO2) is deposited in the trenches between fins, and then etched back to expose some portion of the fins, thus defining the baseline active fin height.

Ideally the fins formed would be vertical and of uniform width (TFIN) to best realize uniform FIN turn-on (from top to bottom of the fin). Practically, however, there are two process issues that drive a need to taper the fins, resulting in ‘triangular’ shapes. The first issue is that the cavities between fins must be filled without forming voids, which necessitates a fin sidewall that is less than 90 degrees. Such voids, if formed, are capable of killing yield (such voids can subsequently fill with either source/drain materials or gate materials, causing short-circuits). The second issue is driven by the need to clear the sidewalls of the fins following (dummy) gate formation, prior to source/drain epitaxial growth. These spacers must be removed from source and drain regions of fins by an anisotropic etch and hence more gently sloped fins, require less over-etch. Some over-etch is always required since any remaining spacer material on an occasional fin can block the formation of the source and drain regions, again killing yield. Extension of over-etch times erodes the isolation oxide adjacent to source and drain fin regions (the channel region is protected by the dummy gate) and hence (vertical) misregistration of the source/drain regions to the gate is worsened, requiring further steps to avoid sub-channel leakage in the fin. The net of this is that a bulk fin employing well/ junction isolation brings with it some intrinsic compromises in fin shape/morphology.

Power/Performance/Leakage Drives Need for Oxide Isolation of Fin

The bulk FinFET includes a ‘sneak path’ from drain to source in a portion of the fin that extends below the channel. Illustrated in Figure 1 are three ‘alignments’ of importance to well-isolated FinFET designs.


Fig1: In Bulk-isolated FinFET CMOS, critical alignments of Source and Drain Depths, Channel Depth, and Gate Depth, to one another, requires challenging integration and manufacturing control. The SOI FinFET provides a near-ideal structure. (Courtesy: IBM Silicon Research and Development Center)

Ideally, the source/drain depth, YSD, the channel-stop depth, YCS, and the gate-edge depth, YGE, would be identical with an abrupt doping step in the fin, just below the gate, to cut off the ‘sneak path.’ Practically, such a structure is not possible, and so, even for an ideal, vertical fin shape, doping in the sub-fin must be sufficiently high to cut off this leakage. In this case one could simply dope the fins uniformly; the doping level required is greater than that needed to achieve a given channel leakage without the sneak path. Penalties for product design, illustrated in Figure 2, ensue.

The maximum operation voltage is limited by maximum allowable electric field in the gate dielectric. Higher doping in the channel results in higher electric fields in operation in a bulk fin, and hence there is an associated reduction in Vmax also illustrated in Figure 2. Additionally, VT variations are increased by this higher doping, and Vmin is increased, for SRAM and other matching-critical circuits. Both ‘Turbo-mode’ performance and low-power mode operation suffer in a bulk-isolated FinFET.

Operating Voltage window

Fig2: • VDD Range is modulated by isolation design
• High channel doping increases RDFs (AVT) → Higher Vmin for SRAM
• High channel doping Increases EOX for given VT → Lower Vmax (BTI and TDDB)
• High AVT also increases Die Iddq for given Ioff → Increased product leakage spec
Operating Voltage window is reduced due to requirements for higher fin doping in bulk-isolated fins vs. oxide-isolated fins. (Courtesy: IBM Silicon Research and Development Center)

Thus far we have taken the case of ideal fin morphology; in practice, bulk-isolated fins present a fin channel with a wider base and the resulting poor gate control requires an even higher doping in this region. The doping at the base of the fin must be sufficient to elevate the local VT by 100-200mV above that of the upper, narrower, portions, in order to avoid excessive device leakage. The output conductance is severely degraded by the delayed, soft turn on of the composite fin. Effective drive current is lost, in this example on the order of 15%, and additionally analog-like high-speed circuits, such as High-Speed I/O are compromised.

The Critical Role of Active Fin Height

Whether on bulk or SOI, FinFETs introduce one fundamentally new behavior for CMOS products, that of (active) fin height (Hfin) variation. In a FinFET transistor, the WEFF varies nearly in proportion to Hfin. Large (wide) transistors will vary in drive strength nearly as much as narrow transistors, since the ‘wide’ FETs simply consist of a larger number of the same base fin. As Hfin varies from die-to-die due to manufacturing variations, the WEFF of  every transistor varies by the same percentage, not the same number of nanometers, as in planar CMOS. This means that active power and performance of a product can be strongly modulated by Hfin, and the tolerances of the bulk manufacturing process can be driven by many challenging-to-control factors, such as across-wafer uniformity, process chamber uniformity, and local design-driven density and proximity issues. The die-to-die variation can appear as an Fmax/Power CLY loss.

SOI as a Means to FOx

While dielectric isolation has been demonstrated on bulk wafers, these schemes continue to lack Hfin control and add cost to the bulk integration for FinFETs. A FinFET process based on an SOI wafer is cost neutral compared to a bulk-isolated Fin with the additional SOI wafer cost easily equaled by the additional bulk process complexity.

SOI offers ultimate Hfin control, with the SOI layer itself defining Hfin. No pattern sensitivities enter, as the active silicon layer is formed unpatterned across the entire substrate. Isolation is automatic and no extra process steps, beyond those required for the transistor formation, are required. Thus within-die and die-to-die variation of Hfin is much less than any currently known alternative, leading to the lowest Vmin, power, and highest Fmax, and CLY for FinFET CMOS.

Misconceptions Surrounding FinFETs on SOI

Strain: Mechanically straining the silicon channels can enhance both hole and electron mobility. Direct techniques for imparting fin strain apply equally to fins on either substrate. One technique employed, embedded SiGe for pFETs, does present a small gain in attainable strain of up to 6% in bulk-fin pFET drive current, amounting to a 3% decrease in a CMOS critical path delay. This gain for the bulk case is, in reality, eroded, if not reversed, by an increase in leakage current from the source/drain region recess beneath the gate, required to realize the added strain. The final result is that an academic gain of up to 3% might be afforded a bulk fin over its SOI counterpart, but when other strain techniques and short-channel degradations are considered, even this benefit vanishes.

Self-heating in SOI FinFETs is very similar to that in planar SOI MOSFETs, and as such, the issues and solutions are well understood at a practical product-applications level. For digital circuits, self-heating is not a consideration, as the short-transient energy dissipated from a single transition is absorbed by the heat capacity of the device with a negligible temperature rise. For circuits in which duty factors are sufficiently high, well-established CAD techniques from planar SOI offer solutions. A narrow sliver of silicon connecting a bulk FinFET to the substrate does reduce the degree of self-heating, but similar CAD requirements in product design remain. Other aspects surrounding self-heating include effects on device and interconnect aging, and here again, the techniques practiced over several generations of planar SOI enable design capability to assure the required product reliability in the field.

Wafer cost and supply: SOI FinFET technology enables a competitive high-volume presence in the market. The steps required to isolate fins on a bulk substrate add considerable complexity and process cost which easily negates any savings in initial wafer cost. Furthermore, the simpler process with SOI FinFETs results in shorter turn-around time. The reduced variability on SOI returns improved yield, and recent announcements by major wafer suppliers have assured a volume supply chain.

SOI Market Value

In addition to the quantitative advantages of SOI-based FinFET described above, the very nature of the near-ideal isolation provided opens many doors to diverse applications. IBM has enjoyed a significant advantage in processors through the integration of embedded DRAM, enabled by SOI isolation, providing 3X net memory density advantage and similar power reduction. RFCMOS, now exploiting SOI in mature nodes, will continue to find high value in SOI FinFETs due to lower parasitic capacitances, reduced (inductive) substrate losses, and radically lower substrate-driven harmonic generation (and other product mixing). A wide range of voltage islands are naturally available, both above and below substrate/ground, without the complexity of triple wells and the restrictions/penalties associated with latch-up avoidance. Automotive, and other very high-temperature environments present no barrier in SOI-based FinFETs.

The value proposition of SOI presented in PDSOI becomes even stronger in FinFET technology, as clearly described above. Furthermore, the design drawbacks of non-standard timing tools and added cost, which presented some barrier in PDSOI vanish as we migrate to FinFET technology, and portability of products from bulk to SOI FinFET designs is very high. As SOC FinFET products are introduced, it is expected that the benefits of dielectrically isolated fins, and in particular, the SOI implementation for this isolation, will prove a clear winner in the market place due to lower variability, lower power, simpler designs and greater flexibility for integration of multiple product needs on chip.

Which wafers for energy-efficient, fully-depleted transistor technologies?

To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.

To continue scaling CMOS technology, new approaches are needed and the industry is turning to ultra-thin body, “fully depleted” (FD) transistors. These may retain a planar architecture (Fig. 1b) or go tri-dimensional (Fig.1c), in which case current flows in vertical ‘fins’ of silicon.

In both cases, in contrast with traditional technology, the current between source and drain is only allowed to flow through a very thin silicon region, defined by the geometry of the transistor. In addition, such transistors can eliminate or alleviate the need for implanting “dopant” atoms into their channel.

The physics of FD transistors allows their behavior to be greatly improved – making it possible to continue creating more complex chips with better performance and, most importantly, with power consumption kept under tight control.

FD transistors

Figure 1: Contrary to conventional CMOS (a), with planar FD (b) and tri-dimensional FD (a.k.a. FinFET) (c), the current is confined within a thin layer of silicon. [notional diagrams – not to scale]

The semiconductor industry is introducing planar FD (also referred to as FD-SOI) starting at the 28nm node, with first IC product samples scheduled for the end of 2012. Tri-dimensional FD or FinFET, on the other hand, is expected below 20nm in foundries.

Wafers for fully-depleted technology

With FD technology, either planar or tri-dimensional, the transistors are either necessarily or advantageously fabricated on innovative silicon-on-insulator (SOI) starting wafers. These wafers consist of a very thin layer of crystalline silicon, separated from a silicon base by a high-quality (and optionally ultra-thin) oxide. Soitec’s Smart CutTM technology is used to produce them and is licensed to third-parties to ensure multi-sourcing options.

Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for the planar and FinFET implementations of FD transistors. Two different wafer product lines are available to serve the needs of these two technology flavors.

FD-2D – An early and evolutionary path to fully-depleted technology

Planar FD technology puts tight requirements upon starting wafers to deliver all its benefits: for example, top silicon layer thickness must be uniform to just a few Angstroms. Today, Soitec’s FD-2D product line meets these needs in a cost-effective way and makes planar FD technology a reality.

Cross-section of a planar FD transistor fabricated on an FD-2D wafer

Figure 2: Cross-section of a planar FD transistor fabricated on an FD-2D wafer [notional – not to scale]

Figure 2 outlines the structure of a transistor fabricated from an FD-2D wafer. For the 28nm technology node, the buried oxide thickness has been set to 25nm; the ultra-thin top silicon allows fabrication of transistors with 5nm to 8nm silicon under the gate. Future generations can leverage even thinner buried oxide layers, contributing to making this technology scalable to subsequent nodes.

By enabling a planar implementation of fully depleted technology, these wafers offer the opportunity to access the benefits of FD today – there is no need to anxiously await FinFET and the 16nm/14nm technology node. Adopters of planar FD are announcing very substantial performance and leakage gains as well as impressive improvements of energy efficiency, along with exceptional performance maintained at very low power supply [Ref.1-3].

Owing to the great compatibility of planar FD with conventional CMOS, designers retain the flows and tools they would use with the latter. Furthermore, chip manufacturers use the same production lines as well as extremely similar process steps. Finally, different studies indicate that the cost of ownership of chips based on planar FD is extremely competitive compared to any alternative.

FinFET – Transition facilitated by innovative FD-3D wafers

A FinFET transistor consists of one or several fins of silicon, electrically isolated from the substrate, around which the gate wraps.

FinFET on bulk silicon wafer

Fig. 3a: FinFET on bulk silicon wafer (one fin shown) [notional – not to scale]

One solution (Figure 3a) to manufacture FinFETs consists of starting from a traditional bulk silicon wafer and completely handling fin creation and isolation through the CMOS process.

FinFET on FD-3D wafer

Fig. 3b: FinFET on FD-3D wafer (one fin shown) [notional, not to scale]

The alternative (Figure 3b) is to start from a “FinFET-friendly” wafer such as Soitec’s FD-3D, which pre-defines some of the fin characteristics and, with its buried oxide, natively embeds the electrical isolation, thus simplifying the CMOS process.

Specifically [Ref. 4-5], FD-3D wafers help obtain clearly defined and reproducible fin height and width, consistent alignment of gate, source, drain and channel, and provide optimal isolation of each fin.  In addition, it is possible to implement undoped fins if desired – thus cutting variability related to random dopant fluctuations.

Overall, and especially as dimensions will continue to shrink beyond the 16nm node, FD-3D wafers offer to facilitate control over key parameters of FinFETs as well as simplify the fabrication process. They represent an opportunity for chipmakers to make the most of FinFET technology in terms of power/performance ratio and leakage power at chip level. They are also a worthwhile proposition to reduce the industrialization challenges and optimize the total cost of ownership.

Longer term

Looking beyond the 10nm node, technology based on germanium and III-V compounds is being actively researched. In parallel, the transition of leading-edge chip production to 450mm diameter wafers is expected for the end of this decade.

In this context, the Smart Cut™ layer transfer technology for manufacturing innovative wafers may again prove extremely valuable by enabling independent control over various optimization knobs. For example, transferring a thin layer of high-quality, optimized III-V material onto a low-cost handle wafer (silicon or other), with an optimized interfacing layer, could be an interesting option.


Fully depleted silicon technology is coming. The question is how fast and how easily this transition can be accomplished: innovative wafers provide part of the answer.

With FD-2D, they enable a planar implementation, providing the semiconductor ecosystem with an early and low-risk path towards optimal performance and power efficiency across all use cases, as soon as the 28nm node.

With FD-3D, they can help efficiently address some key challenges of FinFET technology and make the most of it.

Looking further ahead, the Smart CutTM technology will continue to simplify the implementation of the next silicon technology breakthroughs.


[Ref.1]    White Paper, “Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond”, STMicroelectronics –

[Ref.2]    ST Ericsson Technology Blog, May 2012: “FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2”,

[Ref.3]    “MWC ST-Ericsson Media & Analyst Briefing”, February, 2012 –

[Ref.4]    « SOI Value in IBM Silicon Technology », Oct.2011 – 

[Ref.5]    “SOI versus bulk-silicon nanoscale FinFETs”, Jerry G.Fossum et al., SSE Volume 54, Issue 2, Feb. 2010.

IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm

In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).

For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology.  The industry thus faces a critical juncture in the shrink from 28nm to the nodes around 20nm (the precise dimensions of which vary by foundry).  Making the wrong technology decisions at ~20nm can cost wafer manufacturers and fabless companies billions of dollars.  It is therefore appropriate to analyze the cost factors for the different versions of 28nm as a baseline.

Multiple factors need to be considered with the migration to ~20nm, and the highly visible experience to date in attaining high yielding, volume production on 40nm and 28nm from the industry’s largest players provides visibility into what is likely to happen at 20nm bulk.

IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy.

For the purposes of our analysis, we consider die sizes of both 100mm2 and 200mm2. The flavors we considered are for high-performance (HP) and low-power (LP) chips. The technology options at the 28nm node are high-k/metal-gate (HKMG) bulk CMOS vs. FD-SOI. For the ~20nm node, we add FinFET to the analysis.

Savings realized by using FD-SOI at the ~20nm node

As shown in this graph, the savings realized by using FD-SOI at the ~20nm node is significant. Even once FinFETs have matured in Q1/2016, FD-SOI will still offer comparative savings of 50-60%, depending on die size.

Result: FD-SOI die cost less

At the 28nm node, if you only look at the processed wafer cost, the FD-SOI solutions are roughly 7% higher. However, yield issues and the net die/wafer at 28nm have a major impact on the bottom line. When defect densities and parametric yields are factored in, the FD-SOI solution results in a lower per-die cost: from 8% lower for the smaller, low-power chips, to 18% for large, high-performance chips.

At 20nm, however, the FD-SOI processed wafer cost is less than both bulk CMOS and FinFET processed wafers. The FD-SOI processed wafer cost advantage is then massively increased when yields are factored in.

Once ~20nm bulk FinFETs have matured in Q1/2016, FD-SOI will still offer comparative per-die savings of 50-60%.

Related FD-SOI advantages

Power/performance characteristics of FD-SOI will be 30% to 40% superior to bulk HKMG CMOS at 20nm. Analog porting of FD-SOI will be easier than with the other options because of the superior sub-threshold characteristics.

Today, FD-SOI is the only technology that can operate safely in the 0.6V to 0.7V range at 28nm.  While there is some reduction in performance, operating power is reduced, giving a very compelling performance-power advantage against other technologies.

Although the real competition is likely to be between FinFETs and FD-SOI at 20nm, FinFETs are a new technology (from a high-volume production perspective), with significant cost penalties even in Q1/2016.

Bulk HKMG CMOS will have low parametric yields at 20nm.  A major source of yield loss for bulk CMOS is that of random dopant fluctuations from transistor implants. These implants are not required for FD-SOI.  ~20nm FinFET structures will be high-cost to manufacture, and parametric yields will be low.

The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs.

So compared to bulk CMOS or FinFET, the FD-SOI option cuts ramp time by as much as half.

The faster ramp-up of wafer volumes combined with more predictable yield ramp-up provides additional cost benefits in using FD-SOI over other options at 20nm.

There is ongoing work to assess the further scalability of FD-SOI beyond 20nm to ~14nm and the initial results from IBM and Leti look promising.

Notes on starting parameters

For the purposes of this analysis, the processed wafer costs are derived from experience with leading foundries, for their costs in Q1/13 with eight metal layers (8LM).  (Selling prices of processed wafers will of course be higher and will include the gross profit margins of the foundry vendors.)  The processed wafer costs include $500 for the ultra-thin SOI wafer used in the FD-SOI process, and $129 for the bulk wafer used in bulk CMOS and bulk FinFET technologies. (While there is the expectation that the SOI wafer prices will be reduced in the future, this is not built into our analyses.)

We assume a high-volume production with utilization rates of about 95%. The bulk version assumes three threshhold voltages (Vt) in the core of the chip, and takes into account support for SRAMS and interfaces. The FD SOI cost is based on 1Vt level for the core and use of body biasing. Body biasing can give two additional Vt levels in the core, which is equivalent to bulk CMOS design options.

Wafer and die costs vary at different stages of maturity. For FinFETs, for example, the cost takes into account the relatively long time for metrology checking in the process and also the manufacturing complexity related to the FinFET structures.

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Work at Leti shows that strain is an effective booster for high-performance at future nodes.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Stressor options for FD-SOI technology

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Efficiency of stressor techniques for N & PMOS

Figure 2: Efficiency of stressor techniques for N & PMOS


In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at

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T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

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[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,

A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with

HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.