Category Archive ARM

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

logos_blueIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
Hyatt Regency Monterey Hotel and Spa, Monterey, California
October 7th thru 10th, 2013

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS technology: The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. An additional third track on 3D Integration is also being included, which will emphasize invited talks from world-renowned experts in 3D technology as well as contributed talks from leading research groups and industry.

So all-in-all, attendees can access essentially three conferences with one registration fee, covering three topics at the heart of today’s industry plans:

  • Silicon on Insulator (SOI) – Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-on-Insulator technology, including CMOS, photonics, sensors, NEMS and more. The conference will cover topics spanning from material engineering to circuits and applications, through devices and modeling. There is no better place than this conference to understand the underlying physics of FinFET as fully-depleted devices have always been an important topic.
  • 3D Integration – 3D Integration allows us to scale integrated circuits “orthogonally” in addition to classical 2D device and interconnect scaling. A dedicated session will address the unique features of such stacking with special emphasis on wafer-level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques and bonding methods, as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed.
  • Subthreshold Microelectronics – Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low-power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics.

Conference format

This year, the conference will run two parallel sessions for SOI and Subthreshold Microelectronics. A joint technical session dedicated to 3D integration will also be hosted in addition to the parallel sessions.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

The rump session will lead to lively discussions about the next big changes that will occur in CMOS devices.

Of course, the social events will be maintained as usual. The welcome reception, banquet dinner and cookout are excellent opportunities for people from different backgrounds to meet in a friendly atmosphere, especially this year. There will be specialists from the different fields described above, representatives from established industries as well as startups, professors and scientists from universities and research institutes all over the world. This will be a perfect mix to generate new ideas, start collaborations and initiate new projects.

Optional classes

On top of the regular sessions, this year the conference will offer attendees the possibility to follow one of two different short courses as well as one of two different fundamentals classes.

One short course will focus on 14nm Node Design Methodology (both bulk and SOI, FinFET and planar) and the 3D short course will cover the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects in 3D silicon and packaging.

The SOI fundamentals class will discuss the post-silicon era, including device and material aspects.

The Sub-Vt fundamentals class will cover design techniques for robust sub-Vt operation of integrated circuits. Two key areas will be covered by experts in their fields. First, Professor Massimo Alioto (U. di Sienna, Intel Labs) will instruct attendees on sub-threshold VLSI digital circuits and systems, from microprocessors to memories. Second, Professor Peter Kinget (Columbia U.) will review the challenges for ultra-low-voltage analog and RF circuits and discuss design opportunities to circumvent them. This class is fundamental for anyone considering low-voltage and sub-Vt operation in circuit design.

Location

This year, the conference will take place in the splendid Hyatt Regency Monterey Hotel and Spa, located in Monterey, CA, a beautiful waterfront community on the central coast of California.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

This area offers breathtaking scenery and a profusion of indoor and outdoor activities.

Important dates

Paper submission deadline: 31 May, 2013
Notification of acceptance: 30 June, 2013
Short course date: 7 October, 2013
Conference date: 7 – 10 October, 2013

More details are available on the S3S website.

Bulk logic designs for mobile apps port directly to FD-SOI

Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps.

Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little.

Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of increased performance and decreased power when ported to 20/22nm fully-depleted (FD)-SOI. From the designer’s perspective, the port is essentially direct – really no different from any standard port to a smaller geometry.

Interconnects, routing and RC parasitics are identical. Logic, memories, low- and high-voltage I/O and analog parts are handle in the same way as on bulk. Where there are differences, they are more at the device/process level, and do not pose any particular challenges to the designer at this point. This includes SPICE models, antenna effect, ESD protection, I/O and analog, and back-gate bias.

Synopsys Cadence Magma
Synthesis Design Compiler RTL Compiler Talus Design
Place & route IC Compiler SoCE Nanoroute Talus
Timing analysis PrimeTime (NLDM, CCS) ETS (NLDM, ECSM) Talus (NLDM, CCS)
Power analysis PTPX, PrimeRail (NLDM, CCS) EPS, VoltageStorm Talus
Signal integrity PTSI CeltIC Talus
DFT Tetramax
Verification Formality Conformal

ARM uses standard packages from the leading EDA vendors in SOI ASIC design

20nm FD-SOI v. 28nm Bulk

To get some clear figures on power and performance, ARM recently ported a Cortex-M0 from 28nm bulk to 20nm FD-SOI.  We used the Cortex M0 implementation flow that was proven in 22nm SOI. This included:

  • synthesis, place and route, and the same reduced set of standard cells for 20nm FDSOI and 28nm bulk
  • parasitics extraction for interconnects from the routed 22nm SOI M0 core (22nm SOI Back-End Of Line (BEOL) is considered to be the most representative of current bulk/FD-SOI 20nm BEOL)
  • characterization of 20nm FDSOI and 28nm bulk standard cells (typical process corner and room temperature)
  • different voltages to create the corresponding .lib files that would be used for timing and power analysis of the M0 core: 0.7, 0.8, 0.9 and 1V
  • timings and power were compared for the routed M0 core based on 20nm FD-SOI and 28nm bulk characterizations (.lib).
ARM, 2011 IEEE SOI Conference

Source: ARM, 2011 IEEE SOI Conference

In any next-node port, you typically expect to get a 25% improvement in performance, but in porting from 28nm bulk to 20nm FD-SOI, FD-SOI boosted the improvement far beyond the expected 25%. At a Vdd (supply voltage) of 1.0V, we saw a 40% improvement in performance. At 0.9V, we saw 66%. For Vdd of 0.8, we saw an 80% improvement. And for Vdd of 0.7, we saw an improvement of 125%.

Power is consistently reduced by 30%, and leakage holds steady.

Remember, this is a straight port, which gives us a baseline figure. There are several powerful process and design optimization techniques that can boost those numbers even higher without significantly increasing the complication factor.

Existing design, tremendous results

The conclusions we have drawn are that:

  • a standard bulk ASIC design flow can be used for FDSOI – don’t expect any change
  • an existing bulk logic design can be directly ported to FDSOI
  • you just need to check the timing closure – there is no timing variability (this is not PD-SOI)

FD-SOI should give tremendous advantages in terms of both power and performance. These low-voltage, high-performance chips are perfect for low-power applications, with the undoped channel in the low voltage SRAM resulting in higher margins. For some applications, RF features will also be improved if designers choose high-resistivity substrates.

FD-SOI is all a designer needs for high-performing, low-power mobile applications. And happily from the designer’s point of view, FD-SOI is as simple as designing in bulk.

———-

This article was adapted from “FDSOI Design Portability from BULK at 20nm Node”, which was presented at the 2011 IEEE SOI Conference.

Right Timing

ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.

Input signal testing first and second switch delays starting from DCO or DC1.

SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).

ARM has recently developed new methodology(1) to validate the timing verification for SOI-based chips, and is currently working with foundry clients to tune their SPICE models accordingly.

To maximize accuracy, partially-depleted (PD) SOI timing verification must take into account the “history effect”, wherein the body voltage of a transistor is a function of its recent on/off history. While early SOI adopters had to deal with this on their own, for today’s designers the history effect is just another “corner” accounted for in the physical IP libraries, making it essentially transparent in the design flow.

We have done the work behind the scenes to ensure that both the foundries and fabless designers have models in which they can be completely confident.

Measured and SPICE simulated first switch inverter chain delay.

In the library

For standard cell libraries, ARM characterizes and incorporates timing verification in the library (.lib) files. SOI design requires two libraries per process-voltage-temperature (PVT) corner (whereas bulk silicon design uses one library per corner). For each function, a Max-SOI is characterized for the slowest operation possible, while a Min-SOI library is characterized for the fastest possible operation due to the history effect. The timing analysis tool uses these libraries.

However, it’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.

ARM has developed and proven this reliable timing verification methodology on a 45nm SOI standard cell library. This methodology, which can be applied to any cell, also enables our foundry customers to fine tune their SPICE models, dissociating NMOS from PMOS (rise/fall transition). The same methodology is applied to the 32 and 22nm nodes.

Methodology

The methodology uses both floating-body (FB) and body-contacted (BC) cells (which should not have any history effect at all). It extracts the history effect delay chain timing measurements. Three types of delay chains (FB/FB, BC/BC and FB/BC) are implemented, measured, simulated and compared with a foundry’s actual silicon results.

Essentially, we measure the chain delay of the rise and fall transistions, for the two first switches corresponding to DC0 and DC1 conditions known to deliver the worst case history effect in most cases. We also measure the delays when the steady-state is reached after the signal has been toggling for a long time (typically a few ms).

The measurements are then compared to SPICE simulation results.

Measured and SPICE simulated history effect for rise transition on inverter chain.

Results

Taking one foundry’s BC/BC delay chain as an example, cumulated measurements indicated that 95% of the measurements had a better than 2% accuracy and that the BC chain was exempt of history effect as expected. The silicon measurements were found to be close to the simulation results using the typical process corner. They indicated that the temperature inversion point was close to 0.8V.

A good correlation was obtained between the FB/FB and the FB/BC extracted history effect. However, the simulated history effect spread more than the measured one, which indicated that the SPICE models needed to be retuned to be more accurate in the history effect prediction and then avoid too much pessimism.

ARM helped the foundry retune the SPICE models for greater accuracy. The same methodology has now been used for modeling at the 32nm and 22nm nodes, and for fast and slow process corners.

[1] JL Pelloie et al. Timing Verification of a 45nm SOI Standard-Cell Library. IEEE SOI Conference 2010.

Implementing the 45nm SOI ARM11

The mobile app chip’s 40% power saving was achieved without any major rework in design methodology.

At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.

The goal was to demonstrate the power savings in a real silicon implementation with a well-known, industry-standard core, in an apples-to-apples comparison of 45nm SOI high-performance technology with bulk CMOS 45nm low-power (LP) technology. Read More

Energy-Efficient SoC Design Can Make A Difference

ARM now offers a combination of low-power processors, SOI libraries and power management IP.

It is often the simple actions that make the largest impact when it comes to conserving our natural resources and limiting the negative impact of human interaction on our planet. Conserving our natural and manufactured energy resources is certainly at the top of everyone’s mind.

Now, SoC designers, utilizing the inherent power efficiencies of SOI technology, can make a difference. Read More

2008: ARM Lays the SOI Foundation

This fall, ARM will be rolling out key physical IP libraries, opening the door to broad SOI adoption.

As the leading processor IP company, ARM is collaborating with industry partners to facilitate the adoption of SOI CMOS technology. ARM’s optimized SOI Physical IP libraries target development of high-speed and low dynamicpower SoC designs in 45nm SOI. Read More

SOI for ASICs: Right Into the Flow

Here’s why ARM, the industry’s leading provider of intellectual property for processor, peripheral and SoC design, sees SOI technology as a powerful tool in the quest for optimized performance and power consumption.

Silicon-On-Insulator (SOI) technology offers designers an opportunity for product differentiation and value creation.

Adopting well-designed SOI physical IP products gives ASIC designers additional choices in how they approach higher performance and lower power in a broad range of applications, including mobile, home, enterprise and embedded markets. SOI-enabled choices can help designers create value by differentiating their products and reducing system costs. Read More