Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.
The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.
The complete list of posters and presentations can be seen in the technical program.
This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration. Check the list of participants on those links, and you will see that major players in the field are joining us!
Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.
There will be 2 short courses this year, and 2 fundamentals classes. Those educational tracks are available to you even if you do not register for the full conference.
On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..
Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).
On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.
You could also prefer to take the opportunity to visit the Monterey area.
The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest. The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.
To take full advantage of this outstanding event, register now!
Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.
The latest conference updates are available on the S3S website (http://S3Sconference.org).
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
Hyatt Regency Monterey Hotel and Spa, Monterey, California
October 7th thru 10th, 2013
In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS technology: The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. An additional third track on 3D Integration is also being included, which will emphasize invited talks from world-renowned experts in 3D technology as well as contributed talks from leading research groups and industry.
So all-in-all, attendees can access essentially three conferences with one registration fee, covering three topics at the heart of today’s industry plans:
This year, the conference will run two parallel sessions for SOI and Subthreshold Microelectronics. A joint technical session dedicated to 3D integration will also be hosted in addition to the parallel sessions.
The rump session will lead to lively discussions about the next big changes that will occur in CMOS devices.
Of course, the social events will be maintained as usual. The welcome reception, banquet dinner and cookout are excellent opportunities for people from different backgrounds to meet in a friendly atmosphere, especially this year. There will be specialists from the different fields described above, representatives from established industries as well as startups, professors and scientists from universities and research institutes all over the world. This will be a perfect mix to generate new ideas, start collaborations and initiate new projects.
On top of the regular sessions, this year the conference will offer attendees the possibility to follow one of two different short courses as well as one of two different fundamentals classes.
One short course will focus on 14nm Node Design Methodology (both bulk and SOI, FinFET and planar) and the 3D short course will cover the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects in 3D silicon and packaging.
The SOI fundamentals class will discuss the post-silicon era, including device and material aspects.
The Sub-Vt fundamentals class will cover design techniques for robust sub-Vt operation of integrated circuits. Two key areas will be covered by experts in their fields. First, Professor Massimo Alioto (U. di Sienna, Intel Labs) will instruct attendees on sub-threshold VLSI digital circuits and systems, from microprocessors to memories. Second, Professor Peter Kinget (Columbia U.) will review the challenges for ultra-low-voltage analog and RF circuits and discuss design opportunities to circumvent them. This class is fundamental for anyone considering low-voltage and sub-Vt operation in circuit design.
This year, the conference will take place in the splendid Hyatt Regency Monterey Hotel and Spa, located in Monterey, CA, a beautiful waterfront community on the central coast of California.
This area offers breathtaking scenery and a profusion of indoor and outdoor activities.
Paper submission deadline: 31 May, 2013
Notification of acceptance: 30 June, 2013
Short course date: 7 October, 2013
Conference date: 7 – 10 October, 2013
More details are available on the S3S website.
ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
ARM has recently developed new methodology(1) to validate the timing verification for SOI-based chips, and is currently working with foundry clients to tune their SPICE models accordingly.
To maximize accuracy, partially-depleted (PD) SOI timing verification must take into account the “history effect”, wherein the body voltage of a transistor is a function of its recent on/off history. While early SOI adopters had to deal with this on their own, for today’s designers the history effect is just another “corner” accounted for in the physical IP libraries, making it essentially transparent in the design flow.
We have done the work behind the scenes to ensure that both the foundries and fabless designers have models in which they can be completely confident.
For standard cell libraries, ARM characterizes and incorporates timing verification in the library (.lib) files. SOI design requires two libraries per process-voltage-temperature (PVT) corner (whereas bulk silicon design uses one library per corner). For each function, a Max-SOI is characterized for the slowest operation possible, while a Min-SOI library is characterized for the fastest possible operation due to the history effect. The timing analysis tool uses these libraries.
However, it’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.
ARM has developed and proven this reliable timing verification methodology on a 45nm SOI standard cell library. This methodology, which can be applied to any cell, also enables our foundry customers to fine tune their SPICE models, dissociating NMOS from PMOS (rise/fall transition). The same methodology is applied to the 32 and 22nm nodes.
The methodology uses both floating-body (FB) and body-contacted (BC) cells (which should not have any history effect at all). It extracts the history effect delay chain timing measurements. Three types of delay chains (FB/FB, BC/BC and FB/BC) are implemented, measured, simulated and compared with a foundry’s actual silicon results.
Essentially, we measure the chain delay of the rise and fall transistions, for the two first switches corresponding to DC0 and DC1 conditions known to deliver the worst case history effect in most cases. We also measure the delays when the steady-state is reached after the signal has been toggling for a long time (typically a few ms).
The measurements are then compared to SPICE simulation results.
Taking one foundry’s BC/BC delay chain as an example, cumulated measurements indicated that 95% of the measurements had a better than 2% accuracy and that the BC chain was exempt of history effect as expected. The silicon measurements were found to be close to the simulation results using the typical process corner. They indicated that the temperature inversion point was close to 0.8V.
A good correlation was obtained between the FB/FB and the FB/BC extracted history effect. However, the simulated history effect spread more than the measured one, which indicated that the SPICE models needed to be retuned to be more accurate in the history effect prediction and then avoid too much pessimism.
ARM helped the foundry retune the SPICE models for greater accuracy. The same methodology has now been used for modeling at the 32nm and 22nm nodes, and for fast and slow process corners.
 JL Pelloie et al. Timing Verification of a 45nm SOI Standard-Cell Library. IEEE SOI Conference 2010.
The mobile app chip’s 40% power saving was achieved without any major rework in design methodology.
At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.
The goal was to demonstrate the power savings in a real silicon implementation with a well-known, industry-standard core, in an apples-to-apples comparison of 45nm SOI high-performance technology with bulk CMOS 45nm low-power (LP) technology. Read More
ARM now offers a combination of low-power processors, SOI libraries and power management IP.
It is often the simple actions that make the largest impact when it comes to conserving our natural resources and limiting the negative impact of human interaction on our planet. Conserving our natural and manufactured energy resources is certainly at the top of everyone’s mind.
Now, SoC designers, utilizing the inherent power efficiencies of SOI technology, can make a difference. Read More