Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here).
The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS & sensors), and the SOI manufacturing ecosystem.
The 1st day panel discussion was so interesting we’ll give it a post of its own, then follow up with round-ups of the presentations from both days.
The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF’s CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019.
VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI.
ST Director John Carey noted that ST’s been using FD-SOI since 2014. They’ve fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they’ve got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT.
The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it’s in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded.
Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung’s Lee said they’ve already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST’s Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained.
With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing.
The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung’s seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons.
Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that’s what tier-one players want.
Carey brought it back to RF-SOI (noting that ST’s introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won’t be the bottleneck he said, so what’s the FD-SOI/mmWave roadmap? Kengeri responded that GF’s ready. Lee said Samsung is also ready, and you’d see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it’s qualified. Carey said ST sees it first in consumer premises equipment that’s connected by satellite.
Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn’t give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it’s very important.
In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.
The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.
If you don’t have time to look at all of the ppts, here are quick overviews.
Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:
He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.
Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.
Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:
Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).
This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.
In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.
Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.
K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.
FD-SOI was a very important topic during the recent Mount Qingcheng China IC Ecosystem Forum. To situate things, Mount Qingcheng, with its lush hills and waterways, is located just outside of Chengdu. That of course is where GlobalFoundries is building its new fab, which will be the first in China to run FD-SOI. Chengdu is also a key city in China’s automotive electronics landscape.
The theme of the forum was Building a Smart Automotive Electronics Industry Chain. Over 260 decision-makers from government, academia and industry attended – and the SOI Consortium had a significant presence. The event was chaired by Wayne Dai, CEO/Founder of consortium member VeriSilicon, and tireless champion of the the FD-SOI ecosystem in China and worldwide. Morning keynotes were given by: Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Mark Granger, GF’s VP of Automotive Product Line Management; and Tony King-Smith, Executive Advisor at AImotive, a GF 22FDX customer.
BTW, transcripts of all the talks are available through Gasgoo, China’s largest automotive B2B marketplace. You can click here to access them. (They’re in Chinese – but you can open them in the language of your choice using the major translation websites.)
Fan Yi, Deputy Mayor of Chengdu, spoke extensively of FD-SOI in his keynote on the importance of rapidly developing smart cars.
He heralded the “spectacular” new GlobalFoundries fab there. Following a meeting with the company’s top brass the day before, he affirmed GF’s confidence in their investment. There is a solid roadmap for FD-SOI, he noted, and efforts are underway to accelerate the move into production and expand education and training. He cited the benefits of FD-SOI for the entire supply chain, from design through package and test, raising the level of the entire IC industry to new heights. The government, he said, attaches great importance to this enterprise. Their thinking regarding intelligent transport in China is integrated with the overall approach to smart cities.
In his opening remarks, Wayne Dai emphasized the need for China to seize the advantage in the next round of development opportunities in the automotive electronics industry. This year’s Qingcheng forum, he noted, brought together key representatives from across the supply chain, from of the highest to the deepest reaches of the smart car electronics industry, and across markets, technologies, solutions, industrial ecosystem, standards and regulations.
In his talk on how FD-SOI is boosting the accelerated development of automotive electronics, Carlos Mazure presented the SOI Industry Consortium. He noted that the Consortium promotes mutual understanding and development across the ecosystem. SOI is already present throughout automotive applications, he noted. There are currently about 100mm2 of SOI per car, in such diverse areas power systems, transmissions, entertainment, in-vehicle networking and more. SOI will experience especially high growth in electrification, information/entertainment, networking, 5G, AI/edge computing and ADAS. He then went on to give some history and an extensive overview of the major trends and highlights we’ve seen over recent years. He finished by giving examples of convergence across the supply chain with IC manufacturers working with automakers to lower power, increase processor performance and advance 5G.
GF’s Mark Granger addressed the rapid development of automotive electronics. In certain areas, he said, he sees growth rates of over 20%. They are working on building the Chengdu ecosystem, especially for design, and in cooperation with the rest of the supply chain. Furthermore, he reminded the audience, when you talk about cars, travel implies that you also talk about IoT as well as things like infotainment and integrated radar ICs. In addition to cost and power efficiencies, the AEC-Q100 standard for IC reliability in automotive applications is also pushing designers to turn to FD-SOI. In the GF meeting with Chengdu government officials (referenced above in deputy mayor Fan Yi’s talk), he too confirmed their support of FD-SOI as a key technology for China. GF is currently cooperating with about 75 automotive partners, he said, and the company is looking to increase cooperation with partners in the Chengdu region.
Tony King-Smith talked about the 22FDX test chip AImotive is doing with Verisilicon and GF. In case you missed it, in June 2017 AImotive announced its AI-optimized hardware IP was available to global chip manufacturers for license. AiWare is built from the ground up for running neural networks, and the company says it is up to 20 times more power efficient than other leading AI acceleration hardware solutions on the market. In the same announcement, they revealed that VeriSilicon would be the first to integrate aiWare into a chip design,and that aiWare-based test chips would be fabricated on GF’s 22FDX. The chip is expected to debut this year.
While the afternoon agenda was not specific to FD-SOI, it did focus on the “smart cockpit” and “intelligent driving”, with talks by nine leading players in China’s automotive IC and investment communities.
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Note: Many thanks to the folks at VeriSilicon, who wrote up this event for their WeChat feed, and shared photos with us here at ASN.
Specialty foundry TowerJazz is ramping a 65nm version of its RF-SOI process on 300mm wafers at Fab 7 in Uozu, Japan. To support the ramp, the company has signed a contract with long-term partner, Soitec, guaranteeing a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a tight SOI wafer market.
Five of TJ’s seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch, CEO Russell Ellwanter said in his lead keynote at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai (spring, 2018). BTW, that was in fact a very inspirational talk about Value Creation, and the importance of treating your suppliers with respect. He credited his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity.
“We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF-SOI partnership,” said Soitec CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings.”
According to the TJ press release (you can read it here), with its best in class metrics the TowerJazz 65nm RF-SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals.
It’s a high-growth market, to be sure. Market researchers Mobile Experts predict that the mobile RF front-end market will reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz says its breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards, which will boost data rates and provide further content growth opportunities in the coming years.
Customers are already getting into position. For example, Maxscend (WuXi, China), a provider of RF components and IoT integrated circuits, is ramping in this new technology. “We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Maxscend CEO Zhihan Xu.
As longtime ASN readers will know, we’ve been covering the evolutions of TJ’s RF-SOI platforms since the beginning of the decade. It’s worth noting, too, that beyond RF, TowerJazz also offers foundry customers other SOI-based processes, such as the new 0.18μm BCD SOI, a 200V SOI technology platform (announced in 2017, press release here) for motor drivers, industrial tools, electric vehicles and more. The previous generation 0.18μm SOI for automotive power management also offers exceptional area savings and is well-suited for high temperature operation. Back in 2014, here at ASN we did a great interview with TJ SVP Dr. Marco Racanelli about when and why they use SOI – and while processes have advanced, the basic drivers are still there, so it’s a still a good read.
And finally, designers will want to know that the TJ Multi-Project Wafer (MPW) Shuttle Program offers the 65nm RF-SOI process, as well as other SOI-based processes. See the website for scheduling and details.
That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point.
Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings.
The original goal of the panel was “…to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet ‘always-on’ market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.”
(Update 2 August 2018: a complete video of this panel is now available on YouTube — click here to view it.)
The panelists included:
Brian Fuller of Arm served as moderator.
Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on!
First published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships & Marketing Executive
Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25.
Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what’s not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It’s required innovating throughout the design process including test where Scott said they had create their own “secret sauce” to make it work. Later on in the panel, Scott described designers in near-threshold as “picojoule fanatics” to overcome the limitations in design tools which are geared towards achieving performance goals.
Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design.
Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield.
Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor’s note: sureCore‘s CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.]
Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it’s gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there’s been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future.
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This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original.
* As explained by Rich Collins of Synopsys in the TechDesign Forum: “Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. […] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. […] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.
Per Arm, the industry’s first eMRAM compiler IP is now on Samsung’s 28nm FD-SOI technology. The announcement was made in a post by Kelvin Low, VP Marketing for ARM’s Physical Design Group (read it here). He said that ARM has successfully completed their first eMRAM IP test chip tapeout. The Arm eMRAM compiler IP will be available from 4Q 2018 for lead partners.
Samsung Foundry’s 28nm FD-SOI process technology is called 28FDS. eMRAM (which stands for embedded MagnetoResistive RAM) is a novel non-volatile memory (NVM) option positioned to replace incumbent NVM eFLASH, which has hit its limits in terms of speed, power, and scalability.
Arm’s new eMRAM compiler IP gives Samsung’s 28FDS customers the flexibility to scale their memory needs based on the complexity of various use-cases, explains Low. “What drives the cost-effectiveness of this compiler IP is that eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below,” he says. “Also, the eMRAM compiler can generate instances to replace Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM) and slow SRAM/data buffer memories with a single non-volatile fast memory – particularly suited for cost- and power- sensitive IoT applications.”
At the SOI Consortium’s 2017 Silicon Valley Symposium, Arm said that they were stepping up their support of FD-SOI (read about that here) – and clearly they are! At that event, Arm VP Ron Moore gave a great presentation, which is freely available on our website: Low Power IP: Essential Ingredients for IoT Opportunities.
Samsung, btw, has been offering 28FDS for about three years now. (ASN did a 3-part interview with Kelvin Low back in 2015 when he was a senior director of marketing for Samsung Foundry. It’s still a useful read – you can get it here.) As of last fall, Samsung said it had taped out more than 40 products for various customers. And at the SOI Consortium’s 2018 Silicon Valley Symposium, Hong Hoa, SVP said they’d already taped out another 20 this year (read about that here).
Samsung says the write speed of their eMRAM is 1000x faster than eFlash. They actually announced the industry’s first eMRAM testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here). They also did an eMRAM test chip with NXP. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it above or on YouTube here.)
As noted in ASN’s Silicon Valley 2018 symposium coverage, the basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDS platform will be ready by the end of this year, and eMRAM beginning in 2019.
The CPUs in Summit, the world’s new fastest supercomputer are built on 14nm FinFET-on-SOI technology. Yes, those IBM Power9 CPUs are fabbed by GlobalFoundries (you’ll also find them in the z14, the most recent in IBM’s z-series of servers – a series that’s been on various iterations of SOI since its launch in 2003, btw). Summit’s at the U.S. Department of Energy’s Oak Ridge National Laboratory (ORNL) in Tennessee, USA. It is now the top US supercomputer, and it’s for science.
The IBM-built Summit currently claims the spot in the Top500 as the world’s smartest and most powerful supercomputer. “It is capable of performing 200 quadrillion calculations per second — or 200 petaflops — making it the fastest in the world,” says IBM’s Dr. John E. Kelly, III, SVP, Cognitive Solutions and IBM Research. “But this system has never been just about speed. Summit is also optimized for AI in a data-intense world. We designed a whole new heterogeneous architecture that integrates the robust data analysis of powerful IBM Power CPUs with the deep learning capabilities of GPUs. The result is unparalleled performance on critical new applications.”
And if that’s not impressive enough for you, it’s also #5 on the Green500 list for the world’s most energy-efficient computers, posting Power Efficiency (GFlops/watts) of 13.889.
As GF noted when they announced the technology in the fall of 2017 (read the GF press release here), their 14HP is the industry’s only technology to integrate a FinFET transistor architecture on SOI. Featuring a 17-layer metal stack and more than eight billion transistors per chip, the technology leverages embedded DRAM and other innovative features to deliver higher performance, reduced energy, and better area scaling over previous generations to address a wide range of deep computing workloads.
These technologies have long, deep histories (and were developed in close collaboration with SOI wafer leader Soitec). Here at ASN we have a fabulous archive of pieces contributed by IBM explaining the genesis of the technology – they’re great reads and still entirely pertinent:
As ORNL noted in its press release (you can read it here), the first projects will apply machine learning and AI to astrophysics, materials science, cancer research and systems biology.
BTW, Summit also has a slightly smaller sister machine called Sierra, going in at the Lawrence Livermore National Laboratory (part of the Department of Energy’s National Nuclear Security Administration). With 4,320 nodes (each also containing two 22-core 3.07GHz IBM POWER9 CPUs, which are built on GlobalFoundries’ 14nm HP FinFET-on-SOI technology, but just four NVIDIA Telsa GPUs), Sierra’s claimed the #3 spot on the June 2018 Top500 list of the world’s most powerful supercomputers.
And the Power 9 is now finding it’s way into major data centers – like Google’s (read about that here). There have been some good pieces in the press about it, including in Forbes and The Motley Fool. So yes, clearly there are exciting markets for FinFETs on SOI!
GF’s 22FDX® (22nm FD-SOI) offering is on an automotive roll. The technology platform has been certified for several key automotive standards, and GF has announced an exciting new ADAS customer in Arbe Robotics.
In addition to sharing info from various press releases and blogs, ASN also had a chance to catch up with Mark Granger, GF’s VP for automotive, who provided some great insights. Read on!
When it comes to compliance, automotive industry standards are excruciatingly rigorous. Every part that goes into a car must adhere to the relevant standards: chips are no exception. One such standard is the AEC – Q100, a “Failure Mechanism Based Stress Test Qualification For Integrated Circuits”. The AEC – aka the Automotive Electronics Council – handles those testing standards and certification. Grade 2 means a technology is certified for the -40°C to +105°C ambient operating temperature range. To achieve Grade 2 certification, devices have to successfully withstand reliability stress tests for an extended period of time over the specified temperature range.
GF recently announced that 22FDX has been AEC Q100 Grade 2 certified (press release here). However Granger adds that for their customers, they’ve added additional headroom that takes them to 125°C. They’re now working on Grade 1 certification, he says, which means the devices are certified to handle junction temperatures up to 125°C (and there again, GF has added additional headroom that takes them to 150°C). That should be done by the end of 2018. The ability you get with FD-SOI to tune the transistors using body biasing is really beneficial here, he says.
For GF, the 22FDX qualifications exemplifies their commitment to providing high-performance, high-quality technology solutions for the automotive industry. The automotive industry is driven by a “zero excursions – zero defects” mindset, says Granger, and that drives the foundry, too.
SOI has been used for decades across industries where heat and electromagnetic radiation are challenges, bringing soft error rates (SER) down by orders of magnitude, notes Granger. (SOI, btw, essentially eliminates what are known as Single Event Upsets (SEU) caused by latch-up, which in turn brings down SER.) That in turn, ties into the FIT (failure in time) rate – and that’s part of the ISO 26262 “Road vehicles – Functional safety” standard – where 22FDX is also certified.
As a part of GF’s AutoPro™ platform, 22FDX allows customers to easily migrate their automotive microcontrollers and ASSPs to a more advanced technology, while leveraging the significant area, performance and energy efficiency benefits over competing technologies. Moreover, the optimized platform offers high performance RF and mmWave capabilities for automotive radar applications and supports implementation of logic, Flash, non-volatile memory (NVM) in MCUs and high voltage devices to meet the unique requirements of in-vehicle ICs.
GF’s Fab 1 in Dresden, Germany (which is where they do 22FDX) also has achieved ISO-9001/IATF-16949 certification, which demonstrates that it is capable of meeting the stringent and evolving needs of the automotive industry. (IATF is the International Automotive Task Force. 16949 is a Quality Management System (QMS) certification specifically for the automotive sector.)
Granger wrote a really informative blog on the GF website – you can read it here. It includes this graphic, indicating where in the car 22FDX-based parts are expected to go.
GF recently announced that Arbe Robotics selected 22FDX® as the process technology for its groundbreaking patented imaging radar. Arbe aims to achieve fully automated system capabilities and enable safer driving experiences for autonomous vehicles (read the press release here).
As the first company to demonstrate ultra-high-resolution at a wide field of view, Arbe Robotics’ radar technology can detect pedestrians and obstacles at a range of 300 meters, in any weather and lighting conditions. The processor creates a full 3D shape of the objects and their velocity, and classifies targets using their radar signature.
As Granger noted in his blog, “Radar is one of several sensor types used to detect objects near a vehicle, to enable features like adaptive cruise control. Lidar is another. It uses pulsed lasers to determine distance from an object by measuring the time it takes for the light to reflect back. However, lidar is currently expensive and is affected by weather conditions. Radar is less expensive, and higher-resolution radars promise to compete well with lidar in automotive applications, thereby enabling lower-priced vehicles to enjoy greater ADAS capabilities. 22FDX-based radar sensors can provide higher resolutions and less latency than current radar sensors at a very low total system cost.”
While they may be complementary at first, there is a battle brewing between high-resolution radar and lidar, Granger told ASN. Putting their solution on 22FDX enables Arbe to achieve a 77 GHz mmWave radar and compete cost-effectively with lidar. “They wanted the best,” says Granger. 22FDX can achieve the requisite Ft and Fmax figures of merit. And with transistor stacking, they can also integrate the power amplifier (PA) on a single device. With the low inherent capacitance of the PA in 22FDX, you can get the high power output you need for mmWave but with low power consumption.
GF blogger Dave Lammers has also written a great piece about the Arbe solution (you should read it: here’s the link). “The company said its advanced technology allows the detection of small targets, such as a human or a bike even if they are somewhat masked by a large object such as a truck,” he writes. “The imaging radar can determine whether objects are moving, and in what direction, and alert the car in real-time about a risk.
“While other car sensors can fail when it is raining, if there’s fog, and due to blinding lights such as a sudden reflection, Arbe’s radar is completely oblivious to all those factors. The custom designed radar processor creates a full real-time 4D image of the environment, and classifies targets using their radar signature.”
Avi Bauer, Arbe’s VP of R&D, is now clearly an SOI fan. Lammers quotes him as saying, “With SOI the design is more straightforward, and (voltage) biasing allows you to do things that cannot be done in standard CMOS. For the transmit and receive modules, SOI’s higher resistivity substrate benefits the passive components – inductors and capacitors – and allows good isolation. High Q passives are important. At 22nm, SOI allows better performance overall.”
Clearly good things are coming down the road for FD-SOI!
Some really innovative start-ups presented chips they’re doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We’ll cover those here in Part 3 of ASN’s coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who’s designing chips on FD-SOI, and VLSIresearch explained why. You can read that here.
Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
Ineda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They’re using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes.
In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud.
Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN’s coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor’s talked about their roadmap.
eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July ’18.
Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic.
Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec’s Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting.
In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers & acquisitions would not solve the problem, they’ve opened a second round, targeting another $160 billion.
China’s two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals.
IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said.
The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists.
QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you’ve got one set of IP, and you can decide at runtime where you’re going for low power or high performance. With a lot of power domains, you see the benefits at the system level.
GF VP Dave Eggleston said they’re seeing early adopters of eMRAM, especially for wearables with RF and low power.
ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores.
Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”.
It’s not too late for FD-SOI: it’s perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they’re happy to focus on companies still on the older nodes.
The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You’ve got more potential customers, and your volume runs can be bigger.
In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day’s three take-aways: