Category Archive ASN #14

Driving SOI Cost Reductions
Posted date : Dec 4, 2009

The SOI cost structure is on target for penetrating new markets – especially the all-important mobile markets. Volume customers can anticipat

High volume, high yield production
Posted date : Dec 4, 2009

At the 45nm node, substrate quality and uniformity are more critical than ever before to ensuring the best possible device performance. This is

Increased expectations, drastic reductions
Posted date : Dec 4, 2009

Ultra-low-power design has long been confined to watches, RFID or biomedical niches. But new horizons are opening with the increasing expectati

Understanding SRAM sense amps in SOI design
Posted date : Dec 4, 2009

As the SOI circuit switches, the body voltages of the switching transistors will change from their previous steady state condition. This is cal

SOI’s seven ESD design advantages
Posted date : Dec 4, 2009

SOI technology has some natural advantages in electrostatic discharge (ESD) design. At first glance, many engineers believe that it is a disadv

ESSDERC/ESSCIRC 2009
Posted date : Dec 4, 2009

14-18 September 2009 - Athens, Greece www.essderc2009.org The European Solid-State Device Research Conference (ESSDERC) and the European S

The right choice for 22nm SRAM
Posted date : Dec 4, 2009

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group