Category Archive ASN #3

CELLs Multiply

IBM, Sony/SCEI and Toshiba are actively encouraging the proliferation of CELL applications

 

Some Cell Specs: • Observed clock speed: >4GHz. A wide range of operating frequencies are supported to optimize for power and yield. • Peak performance (single precision): >256 GFlops • Peak performance (double precision): >26 GFlops • Local storage size per Synergistic Processor Unit (SPU): 256KB • Area: 221 mm2 • Technology: 90nm SOI • Total number of transistors: 234M

The most celebrated of Cell applications, Sony’s PlayStation® 3, is due out next spring. In the meantime, the SOI-based Cell Broadband Engine (CBE) microprocessor, as it is officially known, is getting a big push from its joint developers: Sony Computer Entertainment, Inc. (SCEI), Sony, Toshiba and IBM.

From the very beginning, SOI advantages such as higher performance and lower power have been top priorities. “We believe the Cell design, and the advanced technologies like SOI with which it will be manufactured, will help change the way people work, play and communicate”, commented Dr. John Kelly, senior vice president and group executive for the IBM Technology Group.

In a recent IBM developerWorks interview, Power Everywhere™ systems offerings program director Dan Greenberg cited a wide range of potential Cell applications. “High-performance consumer electronics like digital television (DTV) and home media servers, some of which have already been announced by Sony and Toshiba, will use Cell”, he said. He also cited 3D imaging applications such as Magnetic Resonance Imaging (MRI) for medical scanners, CT scanners, ultrasound, radar and sonar, as well as security and surveillance.

A recent Sony statement indicated that the company is creating a division to promote the development of Cell processor-related technology, products and applications, reporting directly to Sony’s CEO. In parallel, Sony and its computer entertainment division are actively courting the PlayStation® developer community. 71 developer/publishers have already signed on to develop over 100 titles. And last fall, SCEI and IBM announced a rack-mount version of a prototype Cell workstation for digital content creation that could hit 16 teraflops.

Toshiba, too, recently announced its Cell Chip Set and Cell Reference Set, putting the emphasis on its powerful broadband capabilities. “Software developers and other customers will be eager to make full use of Cell’s unsurpassed multitasking and real-time processing functions,” said Tomotaka Saito, General Manager of Broadband System LSI Division, Toshiba Corporation Semiconductor Company.

With the Cell heralding the new metric of “performance per watt”, SOI and advanced substrates are poised to enter an array of new markets.

For more information, see:
IBM: www.research.ibm.com/cell
Sony/SCEI: cell.scei.co.jp
Toshiba: www.toshiba.co.jp

SOI in Japan: Full Circle

SOI got its start in Japan. Now in a raft of new applications, its home again

 

Japan’s NTT launched the worldwide SOI revolution 27 years ago when it developed the SIMOX (Separation by IMplanted OXygen) process, and gave the first demonstration of an SOI device. Then, with the advent of wafer bonding and Smart Cut™ technology in the early 1990’s, SOI started reaching beyond niche applications. Read More

Xbox® 360 Debuts New Gaming Generation

Microsoft’s custom PowerPC chip by IBM is based on SOI

 

Microsoft’s Xbox 360, which is expected to fly out of the stores this holiday season, has some very impressive figures to cite. The three-core PowerPC-based CPU, custom-made for Microsoft by IBM, boasts one teraflop of floating-point performance. Read More

Fab Floor Tip: Running SOI in RTP

A quick guide to successful rapid thermal processing of SOI wafers

Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI? Read More

Dawn of a New Age of Chip Technology

Following a long and distinguished career at Sony and Hitachi, an industry visionary reflects on what’s to come

 

For about the past four decades, chip progress was achieved by “shrinking”. Things were simple because three factors – speed, power and density – were improved simultaneously.

In the case of advanced nano devices, leakage current, mobility decrease and wiring delay present additional challenges. New materials and new structures are needed to overcome these drawbacks. Read More

Achieving High Throughput Inspection of Multiple SOI Wafers

Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts.

The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and thickness. This has hampered the ability of chipmakers to establish consistent results at a standard level, and it has also resulted in slower time to results. What chipmakers need in order to accurately and quickly qualify their SOI wafers is a high-throughput capability to inspect SOI substrates, ideally using the same recipe and calibration across multiple wafers. Read More

Soitec and SEZ Collaborate to Speed Industrialization of sSOI

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production

 

Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in sSOI manufacturing. In the sSOI Smart Cut™ process, selectively etching off the germanium template, which is used only to induce the “strain” in the active silicon layer, is a critical step. Read More

NIST Nanowire Transistors on SOI

New design simplifies processing and on/off switching

Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel and the positive and negative electrodes of the transistor. The design allows more electrical current to flow in and out of the silicon, and allows the devices to be switched on and off more easily. The nanowire transistors were made using conventional lithography, indicating that the design will enable the industry to retain its existing silicon technology infrastructure even at nanoscale dimensions.

MIRAI-ASET Working on SGOI and GeOI

3,1 times greater hole-mobility observed in ultra-thin GeOI

 

MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They fabricated an ultra-thin (32nm-thick) GeOI layer by oxidizing a SiGe layer grown on an SOI layer using a Ge-condensation technique. They also fabricated fully-depleted (FD) p-MOSFETs on the GeOI, and observed the hole mobility, which was greater than that of conventional Si p-MOSFETs by 3.1 times.

Soitec President Elected to SEMI Board

Auberton-Hervé joins other prominent industry leaders in representing the interests of material suppliers and equipment manufacturers

 

SEMI recently announced the appointment of André-Jacques Auberton-Hervé to its International Board of Directors. Auberton-Hervé was unanimously elected by the 20 voting members of the association’s board at its recent annual policy and planning meeting. In his announcement, Stanley Myers, president and CEO of SEMI, noted that, “André-Jacques Auberton-Hervé is a recognized technological pioneer and a champion of our industry.” Dr. Auberton-Hervé has a Ph.D. in semiconductor physics and an M.S. in materials science from Ecole Centrale de Lyon (France). He co-founded Soitec in 1992, and currently serves as its President and CEO.