Category Archive ASN #4

Can You Afford Not to Use SOI?

A new Semico Research study estimates the impact of SOI on the bottom line.


As semiconductor process technologies move down the nanometer scale from 90nm to 65nm and smaller, the benefits of silicon-oninsulator (SOI) wafers in reducing junction capacitance, improving the short-channel effect, reducing leakage and decreasing soft error rates become more and more attractive. Although these variables provide a number of advantages for chips requiring high performance at low power, the widespread adoption of SOI wafers still faces both real and perceived challenges. Read More

SOI By Design

The widening availability of tools and services is good news for designers in the fabless/foundry arena considering the move to SOI.

Leading foundries have made the investments in manufacturing on SOI. Those that have taken the final steps – finalizing electrical characterization, constructing SPICE models, integrating design tools and building libraries – are winning business.

Chartered, for example, is producing SOI-based chips for AMD, the Microsoft Xbox®360, Via, and others in partnership with IBM. TSMC, meanwhile has announced an SOI version of its Nexsys 65nm process technology for next year.

For the high-performance fabless community, IBM itself was the first to open SOI doors to its foundry customers. Ghavam Shahidi, Director of Silicon Technology, IBM Research Division, says they see the full range – from customers that do the whole thing themselves, just getting the IBM-specific SOI IP, to those who essentially hand off the whole project to the IBM services group. Asked how big a challenge the move to SOI is, he says, “It’s not a big deal – it seems scarier than it is.”

As far as those low-power customers worried about the added cost of SOI wafers, he suggests that if they were to consider the broader picture and include things like cooling, they might find it a more cost-effective solution.

In the Flow

Design flow involves a series of iterative steps subject to rules and constraints – many of which are different when devices are built in SOI. SOI-specific IP is needed at each step, especially:

• In support of the logic synthesis tools used to transform the high-level RTL design into a gate-level netlist (which is the collection of “standard cells” and their electrical interconnections specific to the foundry that will do the manufacturing).

• And in the placement and routing tools to layout the chip. Either the design team has to develop SOIspecific expertise (a substantial investment), or license intellectual property (IP) from a third party (the foundry or an IP vendor).

By licensing the requisite IP, designing-in SOI becomes a transparent process. As the designer generates netlists and optimizes placement and routing, the SOI IP is applied via standard EDA tools from companies like Cadence, Synopsys and Magna.

TCAD from Synopsys, for example, can model the SOI technology from the process and device simulation standpoint, so performance of SOI and bulk silicon can be compared before choosing the right technology for the design, says a company representative. Also, engineers can optimize the SOI technology by using TCAD simulation before running costly experimental wafers.

Says Francois Thomas, Europe ICD & DFM Field Marketing Director for Cadence Design Systems, “SOI uses nearly standard processes and design but with better performance. The real difference appears for cell creation, analog simulation and DRC and parasitic extraction.”

SOI IP Vendors

Recently three new SOI IP and design services suppliers have helped bring SOI design to a wider community.

Cell layout of SOISIC standard cells library for 90nm SOI process. (Courtesy of Soisic.)

Soisic. Working with companies that pioneered SOI, Soisic developed extensive design expertise and intellectual property (IP), which is now available to any ASIC designer. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed

Innovative Silicon (ISi). ISi has harnessed the SOI “floating body effect” for memory cells that are twice as dense as existing DRAM and five times as dense as existing SRAM. This proprietary “Z-RAM™” (for Zero capacitor DRAM) technology uses standard SOI logic processes without new materials or extra process or masking steps. For most SoC and microprocessor ICs, this results in SOI being a lower-cost solution than bulk silicon. AMD is the first licensee.

CISSOID. As a fabless player, CISSOID designs custom analog, mixed and digital ASICs, with a specialty in SOI-based high temperature components for oil & gas, aeronautics, space and automotive applications. For low-power and RF applications, CISSOID offers design services, IP development and consulting for optimization of SOI analog and RF circuits.

Mixed Signal & RF Choices

For designers of mixed-signal, analog and RF devices, a growing number of major foundries have been actively promoting their SOI services.

For example, Honeywell offers RF SOI foundry services, supported by a comprehensive tool set and optional design services. The company points out that the SOI-enabled integration of mixed signal and high-voltage applications with complex control functions performed at low power on a single chip ultimately reduces cost.

Others like Atmel promote their SOIbased smart power foundry services for automotive, telecommunications and consumer electronics, noting that using SOI cuts the die-area in half compared to standard bulk technology. The X-Fab foundry service offers SOI-based analog/mixed-signal and MEMS.

All things considered, SOI is now well within the grasp of the greater chip design community.

Expert Advice

Michael Gruver, Program Manager, IBM Engineering & Technology Solutions, gives his perspective on foundry customers and custom SOI design.

Advanced Substrate News: What tools or investments would a customer need if they were going for an SOI-based solution?

Michael Gruver: There are two primary areas that a customer should address if they intend to use IBM SOI technology.

The first is SOI-specific design education. SOI has electrical properties that must be accounted for such as the “history effect” and performance variations due to the “floating body” of the SOI transistor. IBM’s Engineering & Technology Services (E&TS) division offers a comprehensive set of education sessions to train individuals in the art of SOI design.

The second area is Tools & Methodology. As industry standard tools cannot directly simulate SOI floating body effects, IBM has a specialized simulator called POWERSPICE that also includes specific functions for analyzing the history effect. Static timing closure with SOI requires special handling. Other more obvious differences include specialized DRC (Design Rules Checking). Once again, IBM E&TS can work with clients to install and train them in the entire flow of tools used for custom SOI design.

ASN: Are there broader benefits beyond the straight performance boost that you tell your customers about that might make that investment worthwhile?

MG: SOI wafers are, in fact, more expensive than bulk. However, there are other variables that can offset this cost, such as smaller die sizes and less complex backend processes. This is especially the case for high-end chip designs where you are trying to gain the maximum frequency.

Of course all of these are trade-offs that need to be carefully understood and weighed. IBM E&TS has consulting services to help you with these decisions.

Via Technologies Extends Range of Ultra-Low Voltage x86 Processors

Fabless Via leverages IBM’s 90nm SOI process.

A leader in the fabless world, Via Technologies has launched its new, fanless 90-nm SOI Via-Eden™ and Eden™ ULV (Ultra Low Voltage) processors, specifically targeted at business, industrial and commercial applications such as thin clients, silent desktops, IPCs and set top boxes where ultra cool, ultra quiet, reliable performance is essential. The chips are manufactured using IBM’s 90nm SOI process.

SOI gets credit for enabling its chips to run 15% faster while using 20% less power, says Via. The reduced die size also enables the company to claim its status as the maker of  the world’s smallest x86 processor die (30mm2), thereby enabling a new generation of small form factor designs and new, smaller applications for the x86 platform.

VIA says its Eden ULV processors set new levels in low power consumption for a fanless processor: the 1.5GHz version draws a maximum of just 7.5 watts, while the 1.0GHz part draws no more than 3.5 watts. The company says this makes them the smallest, most powerful fanless x86 processors on the market.

Via has also announced the SOI-based C7-M ULV processor for ultra compact, ultra portable devices, which the company says features “…the best performance-perwatt operation in the industry.”

More Power to You

Philips is building more and more high voltage/power products on SOI. Here’s why.

Since the 1990’s, Philips has been and continues to be a pioneer in SOI-based high-power and high-voltage ICs (handling anywhere from 12 to 800 volts).

Now these chips are everywhere. They’re in smaller, lighter power modules and battery-chargers for a whole host of products, including PC monitors and peripherals, TVs and set-top boxes, DVDs and CD players, consumer electronics, medical equipment and more. Read More

Benchmarking SOI vs. Bulk Defectivity Levels

Monitoring defects using low thresholds is key to manufacturing yield. For inspecting SOI wafers, UV light overcomes the limitations of visible light. Here’s why.

 

With visible-light inspection tools, the scattering behavior of defects on SOI structures depends on silicon and oxide thicknesses. Because of buried interfaces, transmitted visible light is sent back to the surface after coherent reflection, and can interfere with incoming light. Phase shift of the reflected beam is driven by silicon and buried oxide thickness, resulting in constructive or destructive interferences, increasing or decreasing reflectivity compared to a reference bulk-silicon reflectivity. Scattering intensity on the surface is proportional to the apparent illumination, and depends on structure thicknesses.

Therefore, the only way to implement robust defectivity monitoring using visible light sources is to generate calibration curves for each product generation and SOI thickness. But this is not sufficiently aggressive for sub-90nm technologies.

Using UV light, on the other hand, the transmitted light has to be absorbed before interfering with incoming light at the surface, resulting in constant reflectivity regardless of SOI thickness. Bulk siliconlike metrology can then be implemented on SOI, without additional calibration work for specific SOI films thickness combinations.

With UV defectivity inspection, SOI behaves like bare silicon regardless of the silicon and oxide layer thicknesses. Aggressive thresholds are demonstrated, closing the gaps with industry roadmaps. SOI substrates can be inspected using standard inspection strategies. Similar yields, which have been reported for microprocessor device processing on SOI and bulk, can then be confirmed when benchmarking similar defectivity levels on SOI and epi material, using the same high sensitivity recipe.

Chirac Awards Innovation Prize to Soitec

During an Elysée ceremony, the French president cited the company’s international growth and employment creation.

At a ceremony held at the presidential Elysée Palace in March, French President Jacques Chirac awarded Soitec the “2006 Boldness and Creativity Award” (Prix de l’Audace Créatrice).

The prize, awarded yearly, recognizes the achievements of a listed company that is particularly dynamic, that has posted strong growth and profitability, and also has created significant employment opportunities in France. Initially created in 1995, its goal is to promote the entrepreneurial spirit and support bold initiatives.

Accepting on behalf of the company, Soitec President and co-founder André-Jacques Auberton-Hervé said, “This honor rewards the efforts of everyone at our company – that in less than 14 years, Soitec should become a veritable engine for growth and the top player in its market.”

Soitec was created in 1992 by Jean-Michel Lamure and André-Jacques Auberton-Hervé, two research engineers from the French national CEA/Léti electronics lab, to commercialize Smart Cut™ wafer engineering technology. Listed on the Euronext Paris stock exchange, Soitec posted 04/05 sales of 138.9 million Euros. With sales growing by about 80% in the current fiscal year, the company now counts over 750 employees and an 8% R&D investment rate.

The 2006 Boldness and Creativity Award was chosen by a 14-person jury lead by the Finalac Group, and comprising the presidents of companies such as AXA, Lagardère, Dassault, Group Danone, SEB, Essilor, Club Med and Renault.

IEEE/EDS Accolades for SOI Innovators

Top honors go to advanced substrate pioneers – again.

For the second year in a row, the IEEE Electron Devices Society (EDS) gave the J.J. Ebers Award for “…outstanding technical contributions to electron devices” to an SOI pioneer. The 2005 honor went to Bijan Davari of IBM, now Vice President of Next Generation Computing Systems/Technology.

The awards program noted that Dr. Davari and his team at IBM’s Semiconductor Research and Development Center were responsible for the definition and development of pioneering technologies such as SOI, among their many accomplishments. The previous year’s award went to SOI modeling innovator Jerry G. Fossum.

Another top EDS honor, the George E. Smith Award, went to the MIT and Amberwave team of Zhi-Yuan Charles Cheng, Arthur J. Pitera, Minjoo Larry Lee, Jongwan Jung, Judy L. Hoyt, Dimitri A. Antoniadis and Eugene A. Fitzgerald for their paper entitled, “Fully Depleted Strained-SOI n- and p-MOSFETs on Bonded SGOI Substrates and Study of the SiGe/BOX Interface.” The paper covered FD-SGOI research conducted at MIT.

IBM + SOI Yield More Honors

Company received top White House medal and SI Fab of the Year.

Recently, IBM has been lining up awards for technology leadership, often citing the company’s work in SOI.

IBM’s 300-mm, SOI-enabled Building 323 in East Fishkill, NY, was selected as the Semiconductor International 2005 Top Fab Award winner. According to the publication, “IBM has produced products at competitive cycle times, cost and defect densities, with an excellent ‘first-time-right’ track record.”

At the end of 2005, IBM also received the 2004 National Medal of Technology from the U.S. Department of Commerce and the Technology Administration. The award, which is the nation’s highest honor for leading innovators, recognized IBM for over four decades of innovation in semiconductor technology, specifically citing SOI among the advances.

What’s After Silicon?

For each technology node, those in the substrate world have to be ready with options years in advance of their customers. ASM describes developments in germanium epitaxy that could enable the industry to choose a GeOI future.

In the silicon device industry, new materials have to be introduced to assure IC performance improvement from one technology node to the next.

Soitec’s contribution has been to re-invent the silicon wafer through the development and production of SOI wafers. Most recently, “strained SOI” (sSOI) has been announced, developed in close collaboration with the ASM epitaxy and furnace product groups. sSOI will enable continuous performance improvement from the 45nm node onwards.

In addition to the Soitec “wafer scale” technologies, device and equipment makers have developed local strain processes using selective epitaxy of SiGe for PMOS and most recently also SiC for NMOS.

The Germanium Option
The combination of wafer-scale and local strain can be done up to the point where either the strain effect on the mobility “saturates” or where the strained epitaxial layers start to relax.

At that point, a new material for the channel region becomes unavoidable. The most obvious candidate is germanium because of its much higher mobility for both electrons and holes and because of its chemical similarity to silicon.

However, the worldwide availability of germanium-containing ores is very limited, ruling out a potential change to Ge wafers. To circumvent this limitation, ASM developed an innovative Ge on Si (GOS) process whereby only a thin epitaxial Ge layer is formed on a standard Si substrate.

High quality growth was demonstrated, and further optimization ensured a surface roughness close to what is needed for CMOS processing.

GOS wafers are a natural starting material for Smart Cut™-based manufacturing of Ge on insulator on silicon substrates (GeOI) and can be supplied in any wafer size at much lower cost than Ge wafers. Such layers are now being evaluated not only for CMOS device manufacturing but also for optoelectronic applications.

Also of interest is the fact that Ge can be used as a lattice-matched substrate for GaAs, which has an even higher mobility than Ge. With such a substrate wafer, other III-V materials will become available to integrate unique electronic and optoelectronic capabilities on a Si wafer platform, enabling new device technologies while using cost-effective, large diameter wafers and state of the art production tools.