Category Archive ASN #8

EC Approves €200 Million NanoSmart

Project targets advanced materials for improved performance and electrical consumption.

The Soitec Group, CEA-LETI and the French Agency for Industrial Innovation (AII) have teamed up on a new, €200 million materials research program dubbed the “NanoSmart” project. Nelly Kernevez, a well-known Léti researcher who recently joined Soitec, will head up the project. The European Commission has now authorized the AII to help fund the program. Read More

SOI Technology for Tunable Optical Add-Drop Multiplexers

Pirelli has leveraged SOI and related wafer-level substrate engineering in a new generation of optical telecom components.

Faced with a growing number of bandwidth-hungry applications like IPTV and VoIP, and increasing stress on metro and access networks, optical networking equipment makers need cost-competitive, flexible solutions.

Pirelli Broadband Solutions, the broadband access and photonics company within the Pirelli Group, is leveraging SOI technology and related wafer-level engineering technology, in a suite of tunable components to meet those needs. Tunability helps “future-proof” networking equipment, and makes it much less expensive to operate: updates can be done in software, rather than arduous, disruptive manual manipulations. Read More

Intel’s Approach to Integrated Silicon Photonics

With a goal of driving down the cost of high-speed optical interconnects and communications, the Intel photonics team is leveraging SOI to integrate multiple photonic components onto a single die.

In order to build smaller, faster, and less expensive optical components that fulfill the goal of universal, ubiquitous, low-cost, high-volume optical communications and interconnects, Intel is actively pursuing research work in silicon photonics. Read More

The Path Towards CMOS-Photonics Monolithic Integration

IBM researchers have made strategic advances in key elements needed to achieve on-chip optical networks.

Array of compact silicon photonic microrings of 6 microns radii comprising on-chip all-optical buffers. Results are published in a recent IBM Research paper in the premiere issue of Nature Photonics, January 2007. (Courtesy: IBM Research)

The current trend in the microelectronics industry is to increase the parallelism in computation by multi-threading, by building large-scale multichip systems and, more recently, by increasing the number of cores on a single chip. With such an increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. In particular, massively parallel processing within a multi-core architecture is becoming limited by large power consumption and limited throughput of global electrical interconnects.

To address this issue, the on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. Miniaturization of silicon photonic devices is a key towards practical realization of these ideas.

Photonics wires

Silicon-on-insulator (SOI) technology is ideal for building ultra-dense photonic devices and circuits for an on-chip optical network.

Good optical isolation provided by the micron-thick buried oxide layer (BOX) allows one to shrink the core size of silicon waveguides to submicron cross-sections.

Simultaneously, owing to strong light confinement within a waveguide core, such waveguides, often called photonic wires, can route optical signals over very sharp corners with bending radii as small as just a few microns.

Recently IBM Research has demonstrated that this SOI-based technology opens the way to aggressively scale the footprint of all photonic components required for complex on-chip optical networks down to just a small fraction of a square millimeter. As it is typical in scaled CMOS devices, the power consumption of such devices is also dramatically reduced to sub-milliwatt levels.

Among recent IBM Research demonstrations are:

  • ultra-compact wavelength division multiplexers with footprints as small as 0.004mm²,
  • all-optical buffers having a footprint of 0.05mm² with 10-bit capacity,
  • and ultra-low power optical modulators and switches having smaller than 0.03mm² footprint.

At this level of miniaturization the size of optical components is becoming comparable to the footprint of CMOS devices, suggesting the way towards monolithic integration of advanced CMOS circuits and nanophotonic optical components at the CMOS front-end.

Double-SOI Waveguide:The Communication Pathway Beneath the Surface

Sony is investigating sculpting the waveguide between two layers of buried oxide.

The mainstream of microprocessor research activities has recently moved from increasing clock speed to multiplexing the number of microprocessors. Therefore, communication technology between microprocessors is of great interest in obtaining performance advantages. Read More

The Power of Mobile

The market leader in RF power amps for mobile phones, RFMD is working with Jazz on an SOI-based solution for the next generation of handsets.

RFMD (North Carolina, USA) is a global leader in the design and manufacture of high-performance radio systems and solutions for applications that drive mobile communications. In particular, RFMD supplies nearly 50% of all RF power amplifier (PA) modules used in cellular handsets. Read More

The Power of Communication

Freescale is the world leader in integrated communications processors. Here’s why the new generation PowerQUICC® series is on SOI.

Freescale’s PowerQUICC® family of integrated communications processors go into the world’s leading enterprise routers, wireless LANs, base stations, media gateways, network storage and industrial electronics. For us, that means ensuring the highest level of integration possible with the greatest flexibility to the customer while meeting reliability metrics at the lowest power. Read More

The Promise of High Resistivity SOI for Wireless Communications Systems

ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.

Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.

A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) ( 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications Read More

RF All-In-One

IBM’s new CMOS 7RF SOI technology offers significant cost advantages to designers of mobile handsets.

For mobile phones, laptops and other portable communication devices to reach a broad user base in emerging markets, designers need affordable, power-efficient and high-performance solutions that will further reduce the complexity of components.

To that end, IBM has recently introduced CMOS 7RF SOI technology for our foundry customers. It is designed to enable singlechip RF solutions by integrating the multiple RF/analog functions of today’s handsets – such as multi-mode/multi-band RF switches, complex switch biasing networks, and power controllers – into single-chip solutions for mobile devices.

This new technology provides an integration pathway, enabling designers to integrate filter, power amplifier, power management and receiver/transmitter functions. The breakthrough technology in SOI can minimize insertion loss and maximize isolation to help avoid issues such as loss of signal or dropped calls, potentially enabling significant cost advantages to mobile handsets.

The 180-nm CMOS 7RF SOI is tailored for RF switch applications that provide a low-cost alternative to solutions based on gallium arsenide (GaAs). Initial hardware evaluations have been completed; general availability for design kits is planned for the first half of 2008.

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IEEE Cledo Brunetti Award for Smart Cut™ Inventor

Michel Bruel will be recognized for key SOI substrate technology.

Michel Bruel of the CEA-LETI labs has received notification that he will be the recipient of the 2008 Cledo Brunetti Award, “For inventing Smart Cut layer transfer technology that enabled widespread adoption of SOI for CMOS circuits. ”

The award is presented by the IEEE Board of Directors on the recommendation of the Technical Field Awards Council and the Awards Board, for outstanding contributions to miniaturization in the electronics arts. The ceremony will take place during IEDM in December 2008, which will be held in San Francisco.