Project targets advanced materials for improved performance and electrical consumption.
The Soitec Group, CEA-LETI and the French Agency for Industrial Innovation (AII) have teamed up on a new, €200 million materials research program dubbed the “NanoSmart” project. Nelly Kernevez, a well-known Léti researcher who recently joined Soitec, will head up the project. The European Commission has now authorized the AII to help fund the program. Read More
With a goal of driving down the cost of high-speed optical interconnects and communications, the Intel photonics team is leveraging SOI to integrate multiple photonic components onto a single die.
In order to build smaller, faster, and less expensive optical components that fulfill the goal of universal, ubiquitous, low-cost, high-volume optical communications and interconnects, Intel is actively pursuing research work in silicon photonics. Read More
IBM researchers have made strategic advances in key elements needed to achieve on-chip optical networks.
The current trend in the microelectronics industry is to increase the parallelism in computation by multi-threading, by building large-scale multichip systems and, more recently, by increasing the number of cores on a single chip. With such an increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. In particular, massively parallel processing within a multi-core architecture is becoming limited by large power consumption and limited throughput of global electrical interconnects.
To address this issue, the on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. Miniaturization of silicon photonic devices is a key towards practical realization of these ideas.
Silicon-on-insulator (SOI) technology is ideal for building ultra-dense photonic devices and circuits for an on-chip optical network.
Good optical isolation provided by the micron-thick buried oxide layer (BOX) allows one to shrink the core size of silicon waveguides to submicron cross-sections.
Simultaneously, owing to strong light confinement within a waveguide core, such waveguides, often called photonic wires, can route optical signals over very sharp corners with bending radii as small as just a few microns.
Recently IBM Research has demonstrated that this SOI-based technology opens the way to aggressively scale the footprint of all photonic components required for complex on-chip optical networks down to just a small fraction of a square millimeter. As it is typical in scaled CMOS devices, the power consumption of such devices is also dramatically reduced to sub-milliwatt levels.
Among recent IBM Research demonstrations are:
At this level of miniaturization the size of optical components is becoming comparable to the footprint of CMOS devices, suggesting the way towards monolithic integration of advanced CMOS circuits and nanophotonic optical components at the CMOS front-end.
Sony is investigating sculpting the waveguide between two layers of buried oxide.
The mainstream of microprocessor research activities has recently moved from increasing clock speed to multiplexing the number of microprocessors. Therefore, communication technology between microprocessors is of great interest in obtaining performance advantages. Read More
ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.
Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.
A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) (› 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications Read More
Michel Bruel will be recognized for key SOI substrate technology.
Michel Bruel of the CEA-LETI labs has received notification that he will be the recipient of the 2008 Cledo Brunetti Award, “For inventing Smart Cut layer transfer technology that enabled widespread adoption of SOI for CMOS circuits. ”
The award is presented by the IEEE Board of Directors on the recommendation of the Technical Field Awards Council and the Awards Board, for outstanding contributions to miniaturization in the electronics arts. The ceremony will take place during IEDM in December 2008, which will be held in San Francisco.