The world’s biggest foundry says its 45nm SOI process technology for the newest generation of high performance CPUs is the best in terms of speed, energy and density in chips using standard nitrided oxide for the gate dielectric.
In terms of speed, energy and density, at TSMC we believe we have developed the industry’s best 45nm SOI process technology among all reported MOSFETs with nitrided oxide. The supporting data was presented by our R&D group at IEDM 2007, in a paper entitled 45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application (Samuel K.H. Fung, et al). Read More
CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond.
A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below.
For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than regular Bulk devices. Read More
Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure?
The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the body thickness (TSi) is less than or equal to one-fourth of the gate length (LG). Read More
FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman’s guide to the differences.
Partially depleted SOI has been successfully leveraged for high-performance microprocessors and most other SOI applications for almost a decade. Although OKI has used FD-SOI commercially for a long time, its focus has always been on niche ultra-low power applications. Now, the high-performance world is looking at advanced devices such as ultra-thin body FDSOI MOSFETs and multiple-gate MOSFETs (aka MuGFETs) as potential ways to drastically cut power consumption and leakage while preserving high performance and minimizing short channel effects, probably starting with the 22nm node. See the following graphic and table for an indication of the basic differences between PD and FD SOI.
The ITRS calls for ultra-thin body devices to enter manufacturing in just a few years. The stringent SOI substrate requirements are met with high-volume manufacturing technology.
SOI technology is developing toward Ultra-Thin Body (UTB) semiconductor layers with fully depleted (FD-SOI) and Multiple Gate FETs (MuGFETs), consistent with the latest version of the ITRS.
The current path of scaling bulk and bulklike partially depleted (PD) SOI, while meeting performance, density, and power requirements, becomes exceedingly difficult. Read More
With scaling, SRAM design rules are far tighter than logic. New device structures may be needed.
6T SRAMs are the backbone of embedded CMOS memory. Today SRAMs occupy over 50% of the total chip area. The SRAM cell sizes have been shrinking by ~50% each node. Such aggressive scaling has pushed SRAM design rules far tighter than logic. Read More
Jean-Pierre Colinge brings together work from top researchers in physics, design and fabrication of advanced devices.
Jean-Pierre Colinge has edited a recent addition to Springer’s Integrated Circuits and Systems Series, entitled FinFETs and Other Multi-Gate Transistors. A well-known figure in the SOI world, Colinge brings together chapters contributed by some of the world’s leading experts on multigate FET (MuGFET) technology. In addition to Colinge, contributors include Wade Xiong of TI, Olivier Faynot of CEA-LETI (both of whom also have articles in this current edition of ASN), Chenming Hu of UC Berkeley, and Gerhard Knoblinger of Infineon. Read More
Bernstein and Rohrer’s introduction to SOI device physics and design concepts guides students and engineers through the fundamentals.
Bernstein recalls that when the book was first published and put on sale at ISSCC in 2000, IBM had just announced SOI. At the conference, Bernstein gave a sold-out tutorial. “It was a very exciting time,” he recalls. Read More
Fifteen partners participating in the program recognized for highly successful collaboration on strained SOI.
The European research program SilOnIS, which focused on strained SOI (sSOI), has been honored with the Jean-Pierre Noblanc Award for Excellence. The award is given each year in recognition of the most innovative and sustainable project carried out in the Eureka Medea+ microelectronics cluster of R&D programs. Read More