Category Archive ASN #9

TSMC Reports Industry-Leading Performance

The world’s biggest foundry says its 45nm SOI process technology for the newest generation of high performance CPUs is the best in terms of s

The Promise of FD-SOI for Low Power Applications

CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond. A Fully Depleted SOI CMOS technology has been developed at CEA-LET

Through the Back Gate

Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure? The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has

Fully Depleted (FD) vs. Partially Depleted (PD) SOI

FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman's

SOI Substrates Meet Needs of Advanced Devices

The ITRS calls for ultra-thin body devices to enter manufacturing in just a few years. The stringent SOI substrate requirements are met with hi

OKI: The Industry’s Commercial FD-SOI Pioneer

Since the beginning of the decade, OKI has led the world in the mass production of low-power FD-SOI LSIs for personal and mobile markets. Whil

Challenges Facing Embedded SRAM Scaling for the 32nm Node and Beyond

With scaling, SRAM design rules are far tighter than logic. New device structures may be needed. 6T SRAMs are the backbone of embedded CMOS memo

Industry Experts Contribute to New Book on MuGFETs

Jean-Pierre Colinge brings together work from top researchers in physics, design and fabrication of advanced devices. Jean-Pierre Colinge has ed

Seminal SOI Book from IBM Reissued in Paperback

Bernstein and Rohrer’s introduction to SOI device physics and design concepts guides students and engineers through the fundamentals. Spring

SilOnIS Awarded for Excellence

Fifteen partners participating in the program recognized for highly successful collaboration on strained SOI. The European research prog