Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.
IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.
Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.
The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.
I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.
I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.
One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.
Mark provided a GF link for more information:
Here is the link to our Automotive resources:
One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.
Here is the press release:
Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process
Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs
MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.
“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”
“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”
“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:
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About the Author
Daniel Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”. He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.
GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019.
As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.
The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.
“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”
“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”
As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of.
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*A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago:
Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.
For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering’s Ann Steffora Mutschler from a couple years ago.
Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now.
ArcticPro is the industry’s ﬁrst eFPGA offering for GF’s 22FDX® process (btw they’ve been shipping it in volume for GF’s 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device’s functionality in the field.
QuickLogic has also announced that the technical university ETH Zurich will integrate QuickLogic’s ArcticPro technology onto the university’s PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF’s 22FDX process node. They will develop an SoC integrating ETHZ’s open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption.
“The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” said QuickLogic CTO Dr. Timothy Saxe. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”
ETH’s PULP platform with the fully integrated eFPGA is expected to be available Q1′ 2019.
QuickLogic is part of GF’s fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.
FD-SOI was a very important topic during the recent Mount Qingcheng China IC Ecosystem Forum. To situate things, Mount Qingcheng, with its lush hills and waterways, is located just outside of Chengdu. That of course is where GlobalFoundries is building its new fab, which will be the first in China to run FD-SOI. Chengdu is also a key city in China’s automotive electronics landscape.
The theme of the forum was Building a Smart Automotive Electronics Industry Chain. Over 260 decision-makers from government, academia and industry attended – and the SOI Consortium had a significant presence. The event was chaired by Wayne Dai, CEO/Founder of consortium member VeriSilicon, and tireless champion of the the FD-SOI ecosystem in China and worldwide. Morning keynotes were given by: Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Mark Granger, GF’s VP of Automotive Product Line Management; and Tony King-Smith, Executive Advisor at AImotive, a GF 22FDX customer.
BTW, transcripts of all the talks are available through Gasgoo, China’s largest automotive B2B marketplace. You can click here to access them. (They’re in Chinese – but you can open them in the language of your choice using the major translation websites.)
Fan Yi, Deputy Mayor of Chengdu, spoke extensively of FD-SOI in his keynote on the importance of rapidly developing smart cars.
He heralded the “spectacular” new GlobalFoundries fab there. Following a meeting with the company’s top brass the day before, he affirmed GF’s confidence in their investment. There is a solid roadmap for FD-SOI, he noted, and efforts are underway to accelerate the move into production and expand education and training. He cited the benefits of FD-SOI for the entire supply chain, from design through package and test, raising the level of the entire IC industry to new heights. The government, he said, attaches great importance to this enterprise. Their thinking regarding intelligent transport in China is integrated with the overall approach to smart cities.
In his opening remarks, Wayne Dai emphasized the need for China to seize the advantage in the next round of development opportunities in the automotive electronics industry. This year’s Qingcheng forum, he noted, brought together key representatives from across the supply chain, from of the highest to the deepest reaches of the smart car electronics industry, and across markets, technologies, solutions, industrial ecosystem, standards and regulations.
In his talk on how FD-SOI is boosting the accelerated development of automotive electronics, Carlos Mazure presented the SOI Industry Consortium. He noted that the Consortium promotes mutual understanding and development across the ecosystem. SOI is already present throughout automotive applications, he noted. There are currently about 100mm2 of SOI per car, in such diverse areas power systems, transmissions, entertainment, in-vehicle networking and more. SOI will experience especially high growth in electrification, information/entertainment, networking, 5G, AI/edge computing and ADAS. He then went on to give some history and an extensive overview of the major trends and highlights we’ve seen over recent years. He finished by giving examples of convergence across the supply chain with IC manufacturers working with automakers to lower power, increase processor performance and advance 5G.
GF’s Mark Granger addressed the rapid development of automotive electronics. In certain areas, he said, he sees growth rates of over 20%. They are working on building the Chengdu ecosystem, especially for design, and in cooperation with the rest of the supply chain. Furthermore, he reminded the audience, when you talk about cars, travel implies that you also talk about IoT as well as things like infotainment and integrated radar ICs. In addition to cost and power efficiencies, the AEC-Q100 standard for IC reliability in automotive applications is also pushing designers to turn to FD-SOI. In the GF meeting with Chengdu government officials (referenced above in deputy mayor Fan Yi’s talk), he too confirmed their support of FD-SOI as a key technology for China. GF is currently cooperating with about 75 automotive partners, he said, and the company is looking to increase cooperation with partners in the Chengdu region.
Tony King-Smith talked about the 22FDX test chip AImotive is doing with Verisilicon and GF. In case you missed it, in June 2017 AImotive announced its AI-optimized hardware IP was available to global chip manufacturers for license. AiWare is built from the ground up for running neural networks, and the company says it is up to 20 times more power efficient than other leading AI acceleration hardware solutions on the market. In the same announcement, they revealed that VeriSilicon would be the first to integrate aiWare into a chip design,and that aiWare-based test chips would be fabricated on GF’s 22FDX. The chip is expected to debut this year.
While the afternoon agenda was not specific to FD-SOI, it did focus on the “smart cockpit” and “intelligent driving”, with talks by nine leading players in China’s automotive IC and investment communities.
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Note: Many thanks to the folks at VeriSilicon, who wrote up this event for their WeChat feed, and shared photos with us here at ASN.
GlobalFoundries has announced that the company’s 22nm FD-SOI (22FDX®) technology has delivered more than two billion dollars of client design win revenue. With more than 50 client designs, 22FDX is being used in power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and IoT.
Their clients chose it for the significant reductions in power and die size relative to a traditional bulk CMOS process, says the company. 22FDX offers the industry’s lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, “…providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.”
22FDX is in early production, with yields and performance matching client expectations. A recent VLSI Research survey indicated that FD-SOI technology is seen as a complementary technology to FinFET. It’s gaining traction in application spaces such as IoT, where power consumption is important and the product life is relatively short.
“We’re only just beginning,” said GF CEO Tom Caulfied. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. We will continue to build on our momentum and look for ways to expand our reach to address the evolving needs of the industry.”
Here’s a sampling of customer quotes from the press release (read more here):
GF adds that it is preparing to deliver 12FDX™ technology, which will provide a full node scaling benefit and improved power efficiency for a new generation of applications, from edge-node artificial intelligence and AR/VR to 5G networking and ADAS.
Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.
THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)
“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”
The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.
Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.
The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.
Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.
Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”
GF’s 22FDX® (22nm FD-SOI) offering is on an automotive roll. The technology platform has been certified for several key automotive standards, and GF has announced an exciting new ADAS customer in Arbe Robotics.
In addition to sharing info from various press releases and blogs, ASN also had a chance to catch up with Mark Granger, GF’s VP for automotive, who provided some great insights. Read on!
When it comes to compliance, automotive industry standards are excruciatingly rigorous. Every part that goes into a car must adhere to the relevant standards: chips are no exception. One such standard is the AEC – Q100, a “Failure Mechanism Based Stress Test Qualification For Integrated Circuits”. The AEC – aka the Automotive Electronics Council – handles those testing standards and certification. Grade 2 means a technology is certified for the -40°C to +105°C ambient operating temperature range. To achieve Grade 2 certification, devices have to successfully withstand reliability stress tests for an extended period of time over the specified temperature range.
GF recently announced that 22FDX has been AEC Q100 Grade 2 certified (press release here). However Granger adds that for their customers, they’ve added additional headroom that takes them to 125°C. They’re now working on Grade 1 certification, he says, which means the devices are certified to handle junction temperatures up to 125°C (and there again, GF has added additional headroom that takes them to 150°C). That should be done by the end of 2018. The ability you get with FD-SOI to tune the transistors using body biasing is really beneficial here, he says.
For GF, the 22FDX qualifications exemplifies their commitment to providing high-performance, high-quality technology solutions for the automotive industry. The automotive industry is driven by a “zero excursions – zero defects” mindset, says Granger, and that drives the foundry, too.
SOI has been used for decades across industries where heat and electromagnetic radiation are challenges, bringing soft error rates (SER) down by orders of magnitude, notes Granger. (SOI, btw, essentially eliminates what are known as Single Event Upsets (SEU) caused by latch-up, which in turn brings down SER.) That in turn, ties into the FIT (failure in time) rate – and that’s part of the ISO 26262 “Road vehicles – Functional safety” standard – where 22FDX is also certified.
As a part of GF’s AutoPro™ platform, 22FDX allows customers to easily migrate their automotive microcontrollers and ASSPs to a more advanced technology, while leveraging the significant area, performance and energy efficiency benefits over competing technologies. Moreover, the optimized platform offers high performance RF and mmWave capabilities for automotive radar applications and supports implementation of logic, Flash, non-volatile memory (NVM) in MCUs and high voltage devices to meet the unique requirements of in-vehicle ICs.
GF’s Fab 1 in Dresden, Germany (which is where they do 22FDX) also has achieved ISO-9001/IATF-16949 certification, which demonstrates that it is capable of meeting the stringent and evolving needs of the automotive industry. (IATF is the International Automotive Task Force. 16949 is a Quality Management System (QMS) certification specifically for the automotive sector.)
Granger wrote a really informative blog on the GF website – you can read it here. It includes this graphic, indicating where in the car 22FDX-based parts are expected to go.
GF recently announced that Arbe Robotics selected 22FDX® as the process technology for its groundbreaking patented imaging radar. Arbe aims to achieve fully automated system capabilities and enable safer driving experiences for autonomous vehicles (read the press release here).
As the first company to demonstrate ultra-high-resolution at a wide field of view, Arbe Robotics’ radar technology can detect pedestrians and obstacles at a range of 300 meters, in any weather and lighting conditions. The processor creates a full 3D shape of the objects and their velocity, and classifies targets using their radar signature.
As Granger noted in his blog, “Radar is one of several sensor types used to detect objects near a vehicle, to enable features like adaptive cruise control. Lidar is another. It uses pulsed lasers to determine distance from an object by measuring the time it takes for the light to reflect back. However, lidar is currently expensive and is affected by weather conditions. Radar is less expensive, and higher-resolution radars promise to compete well with lidar in automotive applications, thereby enabling lower-priced vehicles to enjoy greater ADAS capabilities. 22FDX-based radar sensors can provide higher resolutions and less latency than current radar sensors at a very low total system cost.”
While they may be complementary at first, there is a battle brewing between high-resolution radar and lidar, Granger told ASN. Putting their solution on 22FDX enables Arbe to achieve a 77 GHz mmWave radar and compete cost-effectively with lidar. “They wanted the best,” says Granger. 22FDX can achieve the requisite Ft and Fmax figures of merit. And with transistor stacking, they can also integrate the power amplifier (PA) on a single device. With the low inherent capacitance of the PA in 22FDX, you can get the high power output you need for mmWave but with low power consumption.
GF blogger Dave Lammers has also written a great piece about the Arbe solution (you should read it: here’s the link). “The company said its advanced technology allows the detection of small targets, such as a human or a bike even if they are somewhat masked by a large object such as a truck,” he writes. “The imaging radar can determine whether objects are moving, and in what direction, and alert the car in real-time about a risk.
“While other car sensors can fail when it is raining, if there’s fog, and due to blinding lights such as a sudden reflection, Arbe’s radar is completely oblivious to all those factors. The custom designed radar processor creates a full real-time 4D image of the environment, and classifies targets using their radar signature.”
Avi Bauer, Arbe’s VP of R&D, is now clearly an SOI fan. Lammers quotes him as saying, “With SOI the design is more straightforward, and (voltage) biasing allows you to do things that cannot be done in standard CMOS. For the transmit and receive modules, SOI’s higher resistivity substrate benefits the passive components – inductors and capacitors – and allows good isolation. High Q passives are important. At 22nm, SOI allows better performance overall.”
Clearly good things are coming down the road for FD-SOI!
Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It’s that simple. That’s a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium’s 2018 SOI Symposium in Silicon Valley
The afternoon then featured presentations by foundry partners, which I’ll cover here.
Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I’ll cover those in Part 3 of this series.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it.
The presentations are starting to be posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here.
The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they’d consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design.
From a transistor viewpoint, the top reasons to choose FD-SOI is that it’s better for analog and has lower leakage/parastics. It’s perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave.
From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical.
With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company’s foundry business. FD-SOI, he continued, is on a “differentiation path.”
Samsung’s 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They’re seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks.
FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year.
The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.)
The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019.
With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF’s 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan.
Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it’s more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe.
Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they’re already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF’s requirements.
So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
They’ve got initial silicon of Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology, and it’s got record power efficiency (read the full press release here). The chip offers high performance image acquisition and processing capabilities and supports AI / Neural Network (NN) vision operation with a total of 1 TOPS at 500 MHz on 4 parallel engines. With all functions including quad-core Arm® Cortex®-A53, Tensilica DSPs, and INVECAS’ LPDDR4-Interfaces activated, the SoC shows single digit power dissipation without the need for forced cooling, which is of significant importance for embedding in automotive environments.
Targeting automotive computer vision applications, the SoC was created in close cooperation with Arm, ArterisIP, Cadence, GF, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform, where about 40 partners in Europe cooperated to propel the FDSOI-Design Ecosystem.
Of particular importance is the new and reduced power footprint of this SoC in 22FDX-technology from GF. AI/NN-operation for image recognition is available today, but most of the solutions need active cooling. Implementation of Dream Chip Technologies’ SoC on GF’s 22FDX platform demonstrated single digit Watt and cooling targets for designers managing power dissipation. If needed, the SoC bears the potential to increase the performance even further up to 2 TOPS at 1.0 GHz by applying GLOBALFOUNDRIES’s forward body-bias capabilities and other optimization techniques.
The jointly developed ADAS SoC platform from Dream Chip Technologies is available now. Part of GF’s FDXcelerator™ Partner Program, Dream Chip is the largest independent German Design Service company specialized in the development of large ASICs, FPGAs, embedded software and systems with a strong application focus on automotive vision systems (ADAS).