Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.
There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.
SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.
Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
Some really innovative start-ups presented chips they’re doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We’ll cover those here in Part 3 of ASN’s coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who’s designing chips on FD-SOI, and VLSIresearch explained why. You can read that here.
Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
Ineda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They’re using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes.
In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud.
Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN’s coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor’s talked about their roadmap.
eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July ’18.
Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic.
Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec’s Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting.
In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers & acquisitions would not solve the problem, they’ve opened a second round, targeting another $160 billion.
China’s two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals.
IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said.
The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists.
QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you’ve got one set of IP, and you can decide at runtime where you’re going for low power or high performance. With a lot of power domains, you see the benefits at the system level.
GF VP Dave Eggleston said they’re seeing early adopters of eMRAM, especially for wearables with RF and low power.
ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores.
Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”.
It’s not too late for FD-SOI: it’s perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they’re happy to focus on companies still on the older nodes.
The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You’ve got more potential customers, and your volume runs can be bigger.
In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day’s three take-aways: