Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)
At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.
Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.
The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.
We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.
Over the last few weeks there’s been another burst of activity in the FD-SOI arena. A new round of articles, videos and conferences are making FD-SOI the centerpieces. Here’s a quick round-up of things you won’t want to miss.
Info on GlobalFoundries 22nm FD-SOI offering just keeps on coming. Following the ASN roundup of info from the summer and fall (missed it? read it here), they’ve posted yet another excellent FD-SOI video:
How to optimize power and performance with 22FDX™ Platform body-biasing – Dr. Jamie Schaeffer gives a quick (under 3 minute) guide to the basics of front and reverse body-biasing, and the GF approach to a dynamic trade-off between power and performance . He explains how forward body bias (FBB) boosts performance at both high and low voltages, and how reverse body bias (RBB) cuts leakage for the lowest standby power. He also touches on FBB techniques for analog/RF designs.
They’re back! Though they’ve been pretty quiet recently, this latest Samsung video on their 28nm FD-SOI foundry offering hits right at the heart of IoT. Entitled The IoT Revolution and Samsung Foundry’s 28nm FD-SOI, the fun two-minute spot features two runners talking shop during a break. She asks: Is there a lot of design ecosystem support for FD-SOI? He answers: Absolutely. And he goes on to talk about the EDA/IP ecosystem they’re building. It ends on this tantalizing note: He: So you’re done? She: Not! Race you to the next station! He: Oh, it’s on!
With reader interest high and higher, FD-SOI continues to get great coverage in SemiWiki.com. Here are some recent good reads:
IP-SoC Rebound in 2015 ! – IP expert Eric Esteve covers FD-SOI highlights from the upcoming IP-SOC 2015 conference in Grenoble, France (2-3 December 2015), including these presentations (full program here):
28nm FD-SOI: A Unique Sweet Spot Poised to Grow – Pawan Fangaria explains why “…today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on.”
Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node – Tom Simon was at ARM Techcon, where he attended a talk sponsored by Cadence on the topic of using GlobalFoundries 22nm FD-SOI process to implement a quad core ARM Cortex-A17. He shares a number of the key slides in this informative blog.
SemiEngineering Editor-in-Chief Ed Sperling continues his great line-up of incisive interviews. In Increasing Challenges At Advanced Nodes, he gets some spot-on FD-SOI quotes from GlobalFoundries CTO Gary Patton, including:
For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.
And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.
So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.
Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.
For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.
In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.
FD-SOI at the Semicon Europa Low Power Conference
The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conference, which features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.
Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.
Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.
David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)
Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.
Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)
The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).
ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.
Power and 3DI
A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.
Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.
Hope to see you in Grenoble!