Tag Archive design

IBM’s SOI Power

IBM is reaping the benefits of its long SOI history. In 1998, IBM announced that after years of research, it had “pe

SOI and sSOI Address MPU Clock Speed Challenge

IC makers need both local and global strained SOI to win the GHz race. At the device level, the switching speed of MOS

STRAINED SOI

APRIL 2005 - FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform for development of ne

SOI for RF & Low Power ICs

When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These

How to Use SOI for Low-Power Applications

SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already