Tag Archive design

STRAINED SOI
Posted date : Jul 11, 2005

APRIL 2005 - FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform
Posted date : Apr 18, 2005

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform for development of ne

SOI for RF & Low Power ICs
Posted date : Apr 18, 2005

When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These

How to Use SOI for Low-Power Applications
Posted date : Apr 18, 2005

SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already