Tag Archive ETSOI

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications
Posted date : Nov 3, 2014

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM's VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm Fin

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups
Posted date : Feb 4, 2013

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth d

FDSOI Processes are Cost Competitive with Bulk
Posted date : Oct 19, 2011

A new study compares processes for the 20/22nm generation at a typical foundry. Silicon On Insulator (SOI) has been in use for state-of-the-art

SOI at IEDM 2010
Posted date : Jan 24, 2011

The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s

ETSOI Substrates: What We Needi
Posted date : Jul 26, 2010

IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why. ETSOI transist