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4G/5G Opps for SOI Supply Chain – Workshop Presentations Now Posted

The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.

If you don’t have time to look at all of the ppts, here are quick overviews.

Market Overview and FD SOI Opportunities, by Handel Jones, CEO, IBS.

Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:

(Courtesy: IBS and SOI Consortium)

He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.

Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.

Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:

(Courtesy: GlobalFoundries and SOI Consortium)

Empowerment of 5G with SOI-Based Technologies, Emmanuel Sabonnadière, CEO, Leti-CEA.

(Courtesy: Leti and SOI Consortium)

Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).

Engineered Substrates – at the Foundation of 5G, Thomas Piliszczuk, Executive Vice President, Soitec.

This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:

(Courtesy: Soitec and SOI Consortium)

(Courtesy: Soitec and SOI Consortium)

Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.

(Courtesy: Unity and SOI Consortium)

In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.

China 5G Plan and SOI Ecosystem, Jeffrey Wang, CEO, Simgui.

Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.

(Courtesy: Simgui and SOI Consortium)

Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.

(Courtesy: KLA-Tencor and SOI Consortium)

K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.

 

ARM Steps Up! And More Good News From Consortium’s FD-SOI Symposium in Silicon Valley

ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.

The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.

Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.

ARM Pitches In

If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.

CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.

FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF.  ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).

ARM worked with Samsung to compare libraries on 28nm bulk vs 28nm FD-SOI, and came back with these very impressive results. (Courtesy: ARM, SOI Consortium)

The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption.  Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.

In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.

NXP – New Levels in ULP

Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)

NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing.  A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP)  is heading to new levels, he says.

With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.

Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)

Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.

And Much More

Briefly, here are some more highlights.

Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings.  But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.

Dreamchip:  Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI.  One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection.  They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB).  The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.

Dreamchip is using Arteris IP for their ADAS chip in GF’s 22nm FD-SOI (Courtesy: Dreamchip, SOI Consortium)

Greenwaves:  CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros.   The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.

 

Greenwaves expects big power savings in their move to FD-SOI. (Courtesy: Greenwaves, SOI Consortium)

Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.

IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim.  FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.

The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp.  IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled:  lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.

All in all, it was another really good day for FD-SOI in Silicon Valley.

Shanghai FD-SOI and RF-SOI Presentations From Top CEO/CTO/VPs on SOI Consortium Website

A very successful two-day forum on FD-SOI and RF-SOI in Shanghai (September 2015) featured presentations from CEOs, CTOs and VPs at GF, ST, Leti, ARM, Verisilicon, Synapse Design, SITRI, Skyworks, Freescale, TowerJazz, Soitec, Qorvo and many more. Most of the presentations are now available on the SOI Consortium Website, and the rest are expected shortly, so keep checking back.

To download the “Design for FD-SOI” presentations, see the list here.

To download the “RF-SOI Workshop – Interconnected World” presentations, see the list here. (Presentations from all of the major SOI wafer suppliers are also available on this page.)

It’s Official! GlobalFoundries Launches 22FDX: 22nm FD-SOI in 4 flavors

With much fanfare, GlobalFoundries has officially announced its 22nm FD-SOI offering. Dubbed “22FDX™”, GF says the platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar, targeting mainstream mobile, IoT, RF connectivity and networking markets.

Asked by EETimes why FD-SOI here and now, GF’s CEO Sanjay Jha responded, “The mass market is at 28nm/22nm. Really it is leading-edge pure digital that is the niche.” (Read Peter Clarke’s full piece here.)

And so a new paradigm is born.

With FinFETs relegated to the leading-edge-pure-digital niche, GF says FD-SOI provides the best path for cost-sensitive applications (which is everything else, right?!). Their pitch: 22FDX offers the industry’s lowest operating voltage (0.4 volt), enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. Plus it delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

It’s been three years since ST announced (in June 2012) that GF would be providing high-volume sourcing for FD-SOI, but you never saw it on GF’s website — til now. As of 13 July 2015, it’s there in a big way. Today, you can finally go to the GF website and see the headline on the homepage, or find out all about the offer on dedicated tech solution pages (click here to check it out yourself).

GF_FDSOI_website

A snapshot of the GlobalFoundries website page for the new 22nm FD-SOI platform.

GF_FDSOI_apps

Target apps for 22FDX (Courtesy: GlobalFoundries)

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Jha, who was on hand for the big event in Dresden, Germany. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”

And of course it’s good new for the folks at GF’s Fab 1 in Dresden, in the heart of Germany’s “Silicon Saxony” region. GF’s invested another $250 million for technology development and initial 22FDX capacity there (that’s on top of the >$5 billion they’ve invested there since 2009). Further investments to support additional customer demand are planned, plus partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering.

If you read the ASN coverage of the FD-SOI Workshop during LetiDays a few weeks ago, you saw that GF’s 22nm FD-SOI has a 14nm front end and 28nm back end (read it here if you missed it before). At LetiDays, they also talked about body-bias “generators”. In the 22FDX press release they’re referring to it as “…software-control of transistor characteristics to achieve real time tradeoff between static power, dynamic power and performance.”

GF_FDSOI_FBBgraphic

GF slide from 22FDX launch shows the power of forward body-bias (Courtesy: GlobalFoundries)

4 Flavors

Here are the offerings in the 22FDX platform, each one targeting a specific area of applications.

22FD-ulp: ulp aka ultra-low power is an alternative to FinFET for the mainstream and low-cost smartphone market. With body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET, says GF. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.

22FD-uhp: uhp aka ultra-high performance – this offers networking applications with analog integration the capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.

22FD-ull: ull aka ultra-low leakage targets wearables and IoT. It delivers the same capabilities of 22FD-ulp, while reducing static leakage to as low as 1pA/μm (pA = picoamp = one million millionth (10-12) of an amp, folks). This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.

GF_FDSOI_platform

Slide shown during the 22FDX launch summarizes GF’s four FD-SOI flavors. (Courtesy: GlobalFoundries)

22FD-rfa: rfa aka integrated RF and analog. It delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.

GF says they’ve been working closely with key customers and ecosystem partners to enable optimized design methodology and a full suite of foundational and complex IP. Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.

What Customers and Partners are saying

ST: “GLOBALFOUNDRIES’ FDX platform, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum of this technology by expanding the ecosystem and assuring a source of high-volume supply,” said Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”

Freescale: “Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino, vice president of applications processors and advanced technology adoption for Freescale’s MCU group. “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”

ARM: “The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the IP ecosystem needed for customers to benefit from the unique value of 22FDX technology.”

Verisilicon: “VeriSilicon has experience designing IoT SoCs in FD-SOI technology and we have demonstrated the benefits of FD-SOI in addressing ultra-low power and low energy applications,” said Wayne Dai, president and CEO of VeriSilicon Holdings Co. Ltd. “We look forward to collaborating with GLOBALFOUNDRIES on their 22FDX offering to deliver power, performance and cost optimized designs for smart phones, smart homes, and smart cars especially for the China market.”

Imagination: “Next-generation connected devices, in markets from wearables and IoT to mobile and consumer, require semiconductor solutions that provide an optimal balance of performance, power and cost,” said Tony King-Smith, EVP Marketing, Imagination Technologies. “The combination of GLOBALFOUNDRIES’ new 22FDX technology with Imagination’s broad portfolio of advanced IP – including PowerVR multimedia, MIPS CPUs and Ensigma communications – will enable more innovation by our mutual customers as they bring differentiated new products to the market.”

IBS: “FD-SOI technology can provide a multi-node, low-cost roadmap for wearable, consumer, multimedia, automotive, and other applications,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ 22FDX offering brings together the best in low-power FD-SOI technology in a low-cost platform that is expected to experience very strong demand.”

Leti: “FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie-Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES’ 22FDX for connected technologies.”

Soitec: “GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology.”

You might also want to check out GF’s 22FDX brochure (click here to download it) and watch their technical webinar: Extending Moore’s Law with FD-SOI Technology.

Choice is a beautiful thing, don’t you agree?

Tokyo FD-SOI/RF-SOI Workshop (part 1): Samsung, ST presentations & more

A dozen excellent presentations on FD-SOI and RF-SOI were made by industry leaders at the recent workshop in Tokyo. Here in part 1 of ASN’s coverage, we’ll take a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis.

In part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

28FD-SOI: cost effective low power solution for long lived 28nm node by Yongjoo Jeon, Principle Engineer in Foundry Marketing, Samsung

This presentation makes the point that cost and power are equally critical
 factors in the long life foreseen for the 28nm node. (Samsung, of course, is offering ST’s FD-SOI technology on a foundry basis.) In particular, this presentation shows how FD-SOI is especially well-suited for low-power
 IoT apps. (btw, Semiwiki just published an excellent analysis of this Samsung presentation – you can read it here.) The process was successfully qualified in September 2014.

SamsungFDSOI_lowVDD

(Courtesy: Samsung)

SamsungFDSOIprocesscost

(Courtesy: Samsung)

 

FD-SOI advantages for applications and ecosystem by Kirk Ouellette, Director Digital Product Group, STMicroelectronics

As FD-SOI both improves power efficiency and brings high flexibility to SoC integration, this presentation points up the target app benefits:

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

  • For Consumer products, it’s optimized SoC integration with mixed signal and RF; Energy efficiency under all thermal conditions; Optimized leakage in idle mode
  • For IoT, it’s low-cost, ultra-low voltage operation, high scalability and efficient RF and analog integration
  • For networking infrastructure, it’s energy-efficient multicores, effective DVFS and excellent memory performance
  • For automotive, it’s handling leakage at high-temps and high reliability (especially SER re: memory).

RF-SOI: Redefining mobility through the Front End Module by Masashi Arimoto, Technical Executive, Mobile Platform, IBM Microelectronics Japan

In 2006, IBM started transforming a 200mm fab into a specialty foundry. RF-SOI and SiGe were key technologies for cell phone and WiFi front end modules (FEM).  Mobile is key for driving the business of IBM: for infrastructure, for Cloud and for Big Data/analytics. Having shipped over 8 billion RF-SOI chips (>1300 tapeouts) to top mobile customers on its 7RF SOI technology, the company recently announced a new process: 7SW SOI, which packs 30% more performance into a 30% smaller space. They’re seeing ever stronger demand, which IoT will only increase. (Interesting to note that IBM also now sees 300mm FD-SOI as an opportunity for the heart and soul of the cell phone: the application processors.)

(Courtesy: IBM)

(Courtesy: IBM)

RF-SOI and FD-SOI Market Opportunities by Handel Jones, CEO, IBS

Industry guru Handel Jones (read his ASN pieces here) gets into the details of what IoT means in terms of chips, and where and when growth will be happening. Don’t miss his detailed slides on die and wafer cost for the various nodes of FD-SOI, bulk and FinFET (see slides 20-26) – FD-SOI comes out the clear winner in terms of cost benefits. He then explores the various RF segments.

 

ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration by Flavio Benetti, DPG Group VP – Networking Products Division GM, STMicroelectronics

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

Starting with a review of RF trends, this presenation shows how evolutions in the LTE wireless standard for this high-growth market are driving RF Front End Modules (FEM) to unprecedented complexity. ST sees RF-SOI integration as the right answer to that complexity (RF-SOI is of course already the leading technology in smartphone RF switches.) Slide 7 (see illustration) shows the explosive growth in the total annual market (TAM) for RF-SOI wafers. ST’s H9SOI_FEM offering pushes FEM integration to new heights, integrating switching, power amps, antenna tuning, energy management, LNA and filtering, all with best-in-class performance. This is an area in which ST is offering high-capacity foundry services, handling billions of units/year. (ST did an excellent ASN article detailing H9SOI_FEM last year – if you missed it, click here to read it now.)

 

Development of X-ray Sensor with SOI Pixel Technology by Masao Okihara, Device Technology Development Division, Manufacturing Headquarters, LAPIS Semiconductor

This presentation gives on update of the ongoing and fascinating work by a major consortium developing a one-chip monolithic X-ray sensor device on FD-SOI (this was also covered in ASN when the project was first getting underway – you can read that piece here. Oki, which is now Lapis, is providing the foundry services).

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

Successful RF-SOI 2014 International Symposium Held in Shanghai

A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.

The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. ,  a spin-off company from SIMIT,  and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

 

Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)

 

(Courtesy: IBS)

(Courtesy: IBS)

This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.

Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006.  He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)

Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)

Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.

 

The room was full at the Shanghai RF-SOI Workshop 2014

The room was full at the Shanghai RF-SOI Workshop 2014

 

Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.

Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates.  They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate.  (Click here to view the UCL presentation, and here to view the Soitec presentation.)

James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices.  (Click here to view the presentation.)

Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)

RFSOI_Shanghai14_RoundtableDiscussion

Roundtable Discussion at the 2014 International RF-SOI Workshop in Shanghai

The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates.  Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.

 ~ ~ ~

Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original hereMany thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.

Is China Interested in FD-SOI? You bet.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations.

The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM (see below for key slides and links to the full presentations). The goal was to gather IC industry decision makers, technology owners, opinion leaders and market analysts to exchange and assess the opportunities that FD-SOI technology brings in terms of ultra-low power operation at high performance for mobile and IoT.

 

A panel discussion during the SOI Consortium's Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

A panel discussion during the SOI Consortium’s Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

Here are some of the points made by the speakers:

  • FinFET is a tough (Intel is running 15 months behind) and capex consuming technology (exponential situation in terms of costs), so not everybody will be able to go for it
  • FD-SOI will be a game changer
  • the FD-SOI ecosystem is now ready but industry still seems a bit too conservative to get started
  • FD-SOI is a great opportunity for China to take the lead
  • need a big fabless house with a high-volume application and then foundries building capacity
  • promising outlook: designs are underway; in 6 to 9 months there could be significant volumes. It is no longer a question of why FD-SOI – now we are at when FD-SOI.
  • 28nm will be a long lifetime technology node (2012-2024)
  • IoT: a good opportunity for FD-SOI
  • work is being done by the ecosystem to improve FD-SOI IP
  • FD-SOI is not only for 28nm but also 20/22nm and 14nm (ST discussed its 14nm FD-SOI)
  • the industry acknowledges ST and Soitec’s commitment to developing FD-SOI technology

We know that FD-SOI 28nm has moved into the manufacturing and volume production phase. It offers the chip industry the unique features of being able to fabricate at competitive cost, ultra low power, high speed ICs. It is a game changer technology platform that brings new powerful elements to the designers and a strong differentiation potential at IC and system level. But the speakers acknowledged that challenges remain, in particular that there’s a need for a greater commitment from industry and for very big customers (but that’s going to change).

 

The presentations

Here are brief summaries of the presentations. Click on the presentation names to download the full pdfs, or on the slides for enlarged images.

Market Overview and Opportunities by Handel Jones, CEO, International Business Strategies

Starting from a bird’s-eye view of the world, this presentation then zooms down deep into the nitty-gritty of chip manufacturing costs. Considering the various technology options for current and future nodes, it looks at costs per gate and per wafer, costs for design and for tooling, yield impact and fab life. The world’s largest chip consumer, China currently imports about 90% of the chips used there. The government has targeted 2020 as the year by which Chinese semiconductor companies should be supplying 40% of semiconductors consumed in China. IBS sees FD-SOI as the most astute choice, especially for IoT.

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

 

FD-SOI Technology by Laurent Remont, VP Technology & Product Strategy, STMicroelectronics

This presentation gives an overview of FD-SOI technology, roadmaps and markets. One of the points made is that 28nm will be the longest process generation with the highest volume manufacturing. FD-SOI extends the 28nm offering with improved power and performance rivaling existing 20nm bulk.

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

 

Design with FD-SOI, Innovation Through Collaboration by Marco Casale-Rossi, Product Marketing Manager, Synopsys

The Synopsys presentation detailed FD-SOI/EDA readiness, with illustrations from an ST design. Among the many impressive results, time-to-good-floorplan was reduced 10x, and leakage was reduced by 59% through advanced EDA in the flow.

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

 

Designing with FD-SOI for Power Efficiency by Haoran Wang, Associate General Manager, Synapse Design China

Synapse Design is an industry leader in design services for most top tier semiconductor and system companies around the world. They have been working on designs in FD-SOI for over four years. In fact, they’ve already had four tapeouts in FD-SOI and are working on three others. The presentation noted that “…FD-SOI has more degrees of freedom than bulk” conferred by device physics. They recommend starting with a deep power analysis at RTL, looking carefully at performance requirements vs. battery life. They conclude, “At 28nm, FDSOI does show the benefits of speed/power advantage. It is a viable solution from technology point of view and easy to be integrated in current design flow.”

 

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

 

Leveraging FD-SOI to Achieve Both Low Power AND High Speed by Pete Fowley, CEO, Wave Semiconductors

Wave is a fabless semiconductor startup “commercializing a programmable solution addressing power, concurrency, design time, design cost, and deep submicron challenges facing the semiconductor market.” The founders come from a veritable who’s who industry background* (the CEO was one of the first members of Apple’s original Mac chip design team). They bill their FD-SOI based Wave Threshold Logic (WTL) as their “secret sauce”. WTL can use both very fast flip-well LVT devices with Forward Body Bias (FBB) and Standard VT devices that have very low leakage through very high Reverse Body Bias (RBB). According to Wave, “WTL‐ BB represents a unique differentiator for FD‐SOI: enabling significant performance and power advantages over bulk processes. This strategic advantage will persist into deeper nodes.” Clearly one to watch!

 

The FD-SOI Technology for Energy Efficient SoCs by Giorgio Cesana, Director of Marketing, STMicroelectronics

Here ST gives a FD-SOI primer, explaining the technology, design considerations and Forward Body Bias (FBB) use and results. Examples from both fast CPU/GPU and ultra-low power designs are given.

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

SOI Ecosystem – Strategic Opportunity for China by Tom Reeves, VP Technology Alliance, IBM

The SOI ecosystem is a central theme in this presentation. It has a long history of producing successful ICs, and the SOI enabled device structure pipeline continues through 7nm. IBM sees big opportunities for China in mobile, automotive, industrial, IoT, wearable and other More-than-Moore apps. The call to action is clear: now is the time for China to accelerate the building of its SOI ecosystem.

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Foundry Business Opportunities by Paul Colestock, Sr. Director of Segment Marketing, GlobalFoundries has not yet been posted as of this writing. But keep checking back – it should be there soon.

Also, look for another ASN post on the Shanghai 2014 RF-SOI Workshop coming up shortly.

~~

Special thanks to the folks at the SOI Consortium for their help in compiling details for this piece.

* A tip of the hat to Eric Esteve at Semiwiki for first pointing this out in his recent piece on Wave Semi’s technology, which you can read here.

FD-SOI Front and Center at Very Successful Semicon Europa

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).

This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported.  Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.

 Low Power Conference

It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go.  He indicates a major announcement is impending.

 

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk  — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality.  He sees it having a very long life, with monolithic 3D stacking replacing scaling.

The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.

Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers.  His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Shiro Kamohara, Chief Engineer of the Low Power  Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT.  They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share.  For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.

A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said.  He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.

Power (high & smart), power (very low), 3D and more

During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”.  While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%.  Look for more breakthroughs in their paper at IEDM this December, she said.

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)

ST’s FD-SOI demo (Semicon Europa 2014)

ST’s FD-SOI demo (Semicon Europa 2014)

So it was a great show – kudos to the folks at Semi.  Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.

 

Shanghai RF-SOI and FD-SOI presentations being posted on SOI Consortium website

All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.

The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.

The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.

As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.

 

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

(Image courtesy: SEMI)

 

For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.

And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.

So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.

Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.

For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.

In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.

 

FD-SOI at the Semicon Europa Low Power Conference

The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conferencewhich features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.

Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.

Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.

Other talks include imec on FinFETs, Imagination Technology on MIPS, Qualcomm on the “Landscape for More Moore”, and Leti on FD-SOI and 3D stacking for multicore embedded systems.

Renesas will detail their flavor of FD-SOI, which they’ve been working on for a long time (especially with innovations from Hitachi). They call it Silicon-on-Thin-Buried Oxide, aka SOTB.

David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)

Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.

Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)

The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).

ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.

 

Power and 3DI

A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.

Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.

Hope to see you in Grenoble!