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We’re Doing It! FD-SOI Ecosystem Shines in Tokyo (Day 1)

The FD-SOI ecosystem is strong. This was made clear at the recent Tokyo SOI Workshop, organized by the SOI Consortium. The event was spread out over two days, and most of the presentations are now posted (click here to access them).   To cover the full scope of the workshop will take (at least) a couple ASN posts. So let’s start with Day 1, which was billed as the “FD-SOI Ecosystem” day.

A full house for the 3rd Annual Tokyo SOI Workshop, Day 1, FD-SOI Ecosystem(Courtesy: SOI Consortium)

It kicked off with a full-house for an afternoon session in the Yokohama Landmark Tower hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem.

Silvaco:  FD-SOI EDA Pioneer

David Sutton, CEO of EDA provider Silvaco opened the session with his talk, TCAD, EDA & IP to Support FD-SOI. Silvaco has deep FD-SOI roots, having supported Lapis Semi (formerly Oki) in its first forays into the technology – and that was back in 2002! The company is on a growth run this year, having acquired four companies, including IPextreme.

FD-SOI, he said, has been shown to be cost-effective. The capacity is in place, and it’s getting design wins. Silvaco’s full suite of EDA and custom CAD tools for FD-SOI cover the complete design flow from TCAD to sign-off. Their IP is very strong, he said, especially in automotive (including CAN IP), and their partnerships with key players like IBM and NXP are long running. In fact, Silvaco commercializes IP from NXP and others.

GF: FD-SOI Primetime

We got some great insights from Gregg Bartlett, GlobalFoundries’ SVP of the CMOS Business Unit, in his presentation FDX (FDSOI) Goes Mainstream –  Roadmap for Product Competitiveness (it’s posted – click here to download it). “It is primetime for FD-SOI,” he said, and since one technology does not fit all, they’re redefining the mainstream.  GF’s first FD-SOI offering, 22FDX, was qualified in March, and 12FDX will be taping out in the second half of 2018. They’ve currently got over 80 active engagements.

(Courtesy: GlobalFoundries, SOI Consortium)

FD-SOI will be strong in China, he said. GF and the Chengdu municipality recently announced they are investing more than $100 million to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. This will lower the barriers to entry and increase IP availability even further, he said. They’re looking to put 500 design engineers in place. Customer tape-outs of 22FDX will begin at the new fab there in 2H2018, with volume production expected to start in 2019.

He went on to drill down on FDX applications, focusing on four main areas:

  • mobility: application processors that need high performance, RF integration and significant power reduction

  • IoT: this was the target when FDX was first conceived, and it continues to be a point of significant investment by the company

  • RF and mmWave: for BLE (Bluetooth Low Energy), WiFi, ZigBee and integrated PA’s (aka power amplifiers – where they’re seeing some impressive numbers, he said)

  • automotive: Grade 2 is done, and Grade 1 is underway (these are industry ratings related to reliability at the high-temperatures you get under the hood and in hotspots in the passenger compartment).

Citing a slide of customer testimonials, he concluded that the ecosystem is really starting to work, adding that they’ve got the right technology for the right applications, and it’s the right path for them to be on.

Invecas IP & Services

Invecas has been working on 22FDX since 2015 through a strategic partnership with GF. They’ve optimized IP and offer ASIC services, explained Bhaskar Kolla, the company’s Sr. Director of BizDev & Customer Engineering. His presentation, Invecas IP Portfolio in 22FDX is posted – click here to get it. It’s full of detail (standard cells, memories, analog & IO, and interface), so you’ll really want to check it out. The IPs are silicon proven and validated; the results are available, he said.

The foundation IPs are sponsored by GF, so they’re free to customers and cover a broad array of calibrations. They include forward and reverse body biasing (FBB and RBB) and body bias generator IP. Customers are really taking advantage of this, he said, citing as an example one that’s going for 2.5GHz by leveraging FBB.

Custom IP for analog & IO is a place they’re seeing a lot of interest, he continued, and on which they’re doing more and more work with clients. And their Interface IP is in a lot of silicon, especially for customers that are area sensitive. In fact, they’ve developed their own Interface IP demo platform in-house, from build through test and compliance checks.

In moving to FD-SOI, customers are seeing significant PPA improvements, he said. In one of the customer use cases for a high-level IoT product he cited, the customer requirements were easily achieved: cutting leakage in half, dynamic power consumption by roughly a third and area by 20%.

Leti: boosting at 10nm

There’s so much technical detail on performance boosters in Laurent Grenouillet’s presentation, FD-SOI: a Low Power, High Performance Technology Scalable Down to 10nm, you really just have to look at it yourself – click here to get it. A CMOS & Memory Integration Expert at Leti, he did a quick review of 28-22-14nm, then took a deep dive into the myriad of performance boosting options for 10nm, including impressive benchmarking regarding the effectiveness of mobility boosters on FD-SOI vs. FinFET.

Here are the boosters he detailed for 28-22-14nm:

(Courtesy: CEA-Leti, SOI Consortium)

Interestingly he noted that with each node, the thickness of the insulating BOX layer of the SOI wafer scales down, and as it does, back bias efficiency improves even more.

Here’s what he then covered for 10nm (and detailed with data packed in the 20 slides that followed):

(Courtesy: CEA-Leti, SOI Consortium)

FD-SOI is the sweet spot when you need lower power, lower cost, more sensing (analog), more comm (RF), more flexibility and more energy efficiency, he concluded – and he provided powerful data to back that up.

Attopsemi’s non-breaking fuse

I-fuseTM: the best OTP of Choice for FD-SOI and sub-14nm nodes was the topic of a talk by Attopsemi Technology’s Chairman, Shine Chung (you can get the ppt here). The company recently joined GF’s FDXcelerator partner program. OTP stands for one-time programmable memory, and I-fuse is different from other OTP technologies (notably NVM and e-fuses), he explained, in that it’s a non-breaking fuse with ultra-high reliability even in high-temp conditions. It’s been qualified by companies worldwide and is in volume production.

He’s a big fan of FD-SOI because it offers the best RF integration, small form factor, ULP and low cost. Want to make a cellphone as small as a watch? Then you need FD-SOI, he quipped with a tip of the hat to a Dick Tracy image. The fact that FD-SOI has a lower junction breakdown than bulk makes I-fuse the best choice for it, he said. You just program a gate as a fuse.

Get it out the door, fast!

During breaks (on both days!), everybody was talking about the terrific Product Design Methodology presentation by Christophe Tretz, the SOI Consortium’s design guru (and longtime IBM guy). In fact, Christophe has agreed to write it up for ASN in the weeks to come, so don’t miss that. You’ll want to look at the whole presentation — click here to get it.  In the meantime, here are some highlights.

(Courtesy: SOI Consortium)

He suggests designers consider an incremental approach in which FD-SOI benefits accrue. “No, you don’t have to know everything about the technology to use it,” he began (especially addressing those in smaller design teams and houses). “The ecosystem is there. Everything you need to use it is there.”

He used a number of cases to explain.

  • Case 1: a simple, digital SOC – you get significant power savings just by reusing existing library blocks and doing minor recompile.

  • Case 2: RF/mixed-signal – turnaround time is very fast (Analog Bits, for example cut leakage by 5x in a port that took just three months). FD-SOI gives analog designers a great new thing to play with for big power savings – and they learn fast.

  • Case 3 (= Cases 1 + 2): “complex” SOC with RF blocks – rework the RF blocks, but reuse library elements for the digital part without a lot of design effort. You get significant power savings very easily.

  • Case 4: a more complex SOC – in this case, you optimize or customize a few blocks in the first design pass, but then optimize/customize more blocks in subsequent design passes. It just keeps getting better and better.

  • Case X: a fully optimized SOC. This takes more time, but you can do parts in parallel and get dramatic results – especially if you use body biasing.

He then looked at the state of the ecosystem:

  • three fabs are ready

  • we have the tools (Synopsys, Cadence, Silvaco)

  • the libraries are there and ready to use

“You don’t have to learn everything to get your product out the door,” he concluded. “You don’t have to do it all at once: you can do it incrementally. Within a few months, you’ll have a nice product, and as you do new products every six months, each time you can re-use, but also tune for more improvements.”

In short: just do it!

So that’s a recap of Day 1. Next post (or posts?) I’ll recap Day 2. Stay tuned!

Upcoming SOI/FD-SOI Workshop in Tokyo – Great Line-Up, Registration Still Open

Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.

This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.)  You’ll find the full program here. A brief summary follows.

(©Tokyo Convention & Visitors Bureau)

Day 1

The first day – Wednesday, May 31st  – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.  

It will take place on the 25th floor of the Yokohama Landmark Tower.  The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.

Day 2

The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.  

It kicks off with talks on ultra-low power applications from Sony IoT and Samsung.  Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure.  The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.

Coffee breaks and lunch will give attendees and speakers time for further discussion.

This is a great opportunity – don’t miss it!

ARM Steps Up! And More Good News From Consortium’s FD-SOI Symposium in Silicon Valley

ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.

The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.

Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.

ARM Pitches In

If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.

CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.

FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF.  ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).

ARM worked with Samsung to compare libraries on 28nm bulk vs 28nm FD-SOI, and came back with these very impressive results. (Courtesy: ARM, SOI Consortium)

The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption.  Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.

In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.

NXP – New Levels in ULP

Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)

NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing.  A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP)  is heading to new levels, he says.

With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.

Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)

Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.

And Much More

Briefly, here are some more highlights.

Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings.  But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.

Dreamchip:  Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI.  One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection.  They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB).  The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.

Dreamchip is using Arteris IP for their ADAS chip in GF’s 22nm FD-SOI (Courtesy: Dreamchip, SOI Consortium)

Greenwaves:  CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros.   The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.

 

Greenwaves expects big power savings in their move to FD-SOI. (Courtesy: Greenwaves, SOI Consortium)

Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.

IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim.  FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.

The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp.  IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled:  lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.

All in all, it was another really good day for FD-SOI in Silicon Valley.

12nm FD-SOI on the Roadmap for H1/2019 Customer Tape-out! Says GloFo (While Giving 22FDX Ecosys a Great Boost)

gf_logo12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).

gf_12fdxslide16lowres

(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology.  “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”

The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

All About 12

GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.

The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.

gf_12fdxslide20lowres

(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).

22 Design Plug ‘n Play

Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.

Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  • tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  • a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology; and
  • product packaging and test (OSAT) solutions.

Additional FDXcelerator members will be announced in the following months.