There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks.
They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we’ll keep you posted (and of course, keep checking back for news on the Consortium’s Events page).
The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai.
Just to put this in perspective, SIMIT and SITRI are absolutely key players in China’s chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world’s earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China.
At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu.
The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman & Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.”
The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries.
After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology.
The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored.
The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers.
Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI.
“The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.”
“The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design & Technologies.
“The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design & Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.”
The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed.
“As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)
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ASN: Let’s talk a little more about IP availability.
Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.
Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.
ASN: In terms of the ecosystem, what remains to be done?
KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.
KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.
As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.
ASN: Any closing thoughts?
KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.
This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).
Mentor Graphics is collaborating with GlobalFoundries on 22nm FD-SOI to qualify the Mentor® RTL to GDS platform for the current version of GlobalFoundries 22FDX™ platform reference flow. (Read the press release here.) This includes including Mentor’s RealTime Designer™ physical RTL synthesis solution and Olympus-SoC™ place & route system. In addition, Mentor and GF are working on the development of the Process Design Kit (PDK) for the 22FDX platform. The PDK includes support for the Mentor Calibre® platform, covering design rule checking (DRC), layout vs. schematic (LVS) and metal fill solutions for 22FDX. These solutions help mutual customers optimize their designs using the capability of 22FDX technology to manage the power, performance and leakage.
“We are collaborating closely with Mentor Graphics on enabling their products to help customers realize the benefits of the 22FDX platform,” said Pankaj Mayor, vice president of Business Development for GlobalFoundries. “The qualification of Mentor tools for implementation flows and design verification will help designers to achieve an optimal balance between power, performance and cost.”
The next release of the 22FDX PDK will put GF’s differentiated DFM capabilities into the hands of designers, says a Mentor spokesperson, ensuring delivery of high-quality designs and ensuring faster ramps to production.
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)
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ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?
Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.
Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.
Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.
ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?
KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.
Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.
KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.
ASN: Can designers get started today?
KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.
Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.
There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.
ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.
KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.
FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.
There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.
AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.
ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?
KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.
AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.
KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
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This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).
ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.
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ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?
Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.
What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.
Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship
KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.
We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.
ASN: Do you have other customers lined up?
KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.
ASN: What about technology readiness and maturity?
KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.
This slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.
ASN: When will we see the first high-volume FD-SOI chips? Next year?
KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.
AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.
KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.
[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]
KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.
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CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. In 2013, they had 32 prototypes from 15 customers over three runs. The latest run embedded 25 different projects. Delivery of that run to users will be in Q2 2014.
“We have a total of 140 institutions/companies already using the PDK. Four MPW runs are scheduled in 2014, one for each quarter,” said Dr. Torki. MPW price is 15000 Euro/mm2.
“At CMP we fully support UTSOI model cards available in the process design-kit (PDK) for the 28nm FDSOI process,” explains Dr. Torki. The simulation model itself is available for Eldo, Spectre and Hspice. Cadence, Mentor and Synopsys make this model available as a standard feature thanks to a Leti-ST licensing agreement.
Look for news about availability of Leti’s new UTSOI2 model (click here for more information on the model) for 14nm FD-SOI in Q2.
2014’s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise.
But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year. In fact, there was so much happening that we’ll review 2013 in two posts – this post is about FD-SOI; in the next post we’ll cover RF-SOI and FinFETs.
Highs, lows, and the promise of an extra day
It was just a year ago that you read in the first ASN post of 2013 about ST-Ericsson’s NovaThor™ L8580 ModAp: at 2.5GHz it was “the world’s fastest and lowest-power integrated LTE smartphone platform” at CES ’13 in Las Vegas. Then in February in Barcelona ST announced that its 28nm FD-SOI technology clocked in at 3GHz, but what was really amazing was that it got 1GHz using using just 0.6V VDD, aka the “supply voltage”, which is the main voltage “in” that powers the chip. No one had been able to run stably on that low a voltage before. 28nm FD-SOI got you a full extra day before you had to recharge your device.
But then of course came the sad news that the plug was pulled on ST-E. Happily the technology moved into the ST fold, and the 28nm process is now ramping in volume, with 14nm is set to debut shortly.
May was a big month. ST’s FD-SOI got the EETimes ACE Award for Energy Technology – and the company announced it had started winning FD-SOI customers. We also got the news of a big public-private funding boost, to the tune of €360M, for the Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe). It is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL. A 3-year public-private project involving 500 engineers from 19 members in seven countries, it’s looking to enable volume manufacturing in Europe from 28nm down to 10nm.
Also in May, Leti told us that they’d gotten silicon layers down to 3.5nm, and for boosting pFETs with SiGe, were seeing better results with FD-SOI than bulk FinFETs. What’s more, they found that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
In August, the French government upped the ante with a 600 million Euro investment in the Nano2017 program, which was in addition to the 3.5 billion Euros that ST and partners had already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).
In October, Leti said it would have the 10nm FD-SOI PDK ready in June of 2014.
In November, the wafer supply chain got a boost when SOI wafer suppliers Soitec and SunEdison (formerly MEMC) ended their longstanding legal feud and entered into a patent cross-license agreement.
At IEDM in December Leti announced UTSOI2, a compact model for electrical simulations. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers use before they run silicon. Dedicated to Ultra-Thin Body and Box (UTBB) FD-SOI technology, UTSOI2 accurately describes independent double gate operation for sub-20nm nodes. Also at IEDM, ST, Leti, IBM, Renesas, Soitec and GlobalFoundries presented the big paper showing great results for 14nm FD-SOI.
So 2014 promises to be an excellent year. Stayed tuned – next up we’ll review the great strides made in RF-SOI and SOI-FinFETs.
From all of us here at ASN, wishing you a safe, happy, healthy, prosperous and innovative New Year!
A blog on the Mentor website entitled the Battle of Fins and BOXes considers FD-SOI, FinFETs and planar bulk. The author notes, “Power/performance claims of 30% to 40% are not uncommon and FDSOI is already in production at 28nm and is positioned as an alternate option to bulk 20nm. Even if FDSOI at 28nm delivers half the power savings of bulk 20nm, I would take it any day rather than dealing with the beast that is Double Patterning. I digress. One of the other untold benefits from a P&R perspective is that the FDSOI technology can use the conventional design flows and is completely transparent to the tools.”
STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.”
Can they do it?
Yes, they can.
Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and love. Although the concept is over a decade old, the current technical development is moving at lightspeed.
When ST ported 28nm bulk to 28nm FD-SOI, they did it soup-to-nuts – including wafer processing – in under six months, with amazing results. At VLSI Kyoto, they reported that starting from a direct porting of a bulk planar CMOS SRAM design, the improvement in read current Iread was up to +50% (@Vdd=1.0V) and +200% (@ Vdd=0.6 V), respectively, compared with the original 28nm Low-Power (LP) CMOS technology.
The laying of the foundation – writing compact and SPICE models – has long been done. As Leti’s Olivier Rozeau explained in his article about Leti’s 28nm FD-SOI Compact models a few years ago in ASN, robust models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to committing a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
And when Mentor moved the Leti models to robust circuit simulators, they did it in under two years. Phenomenal! Leti’s 14nm models are now done, and the PDKs will be ready in Q3’13.
In fact, Leti is now working on models for 10nm FD-SOI, for which they’ll have PDKs in a year. That means all systems are go for 10nm FD-SOI in 2016. (And by the way, Leti CEO Laurent Malier also says that for boosting pFETs with SiGe, they’re seeing better results with FD-SOI than bulk FinFETs.)
What about manufacturing? Fabs typically take about a year to re-characterize their processes for a shrink. Moving from planar 28nm to 14nm FD-SOI is a straight shrink of what is essentially a legacy technology. Again, no showstoppers.
From a manufacturing standpoint, there are no gotchas, no special equipment. As Chery noted in an ASN interview last fall, “On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.”
The ultra-thin wafers have been ready for years, and have multiple sources including Soitec and SEH.
In terms of design, the design flows, methodologies and tools are the same as designers have always used. And, with FD-SOI, biasing efficiency (not possible in FinFETs) is an added bonus. ST has published figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at low power 0.6V – especially good news for anything with a battery.
In fact, Leti’s Malier recently highlighted that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
Leti’s finding that boosters like strain add another 10% to the performance figures: so overall with boosters they’re seeing +40% performance at the same supply voltage (Vdd) moving to 14nm, and another 30% moving to 10nm.
In discussing the two flavors of FD-SOI they have planned, Subi Kengeri, Vice President of Advanced Technology Architecture at GlobalFoundries points to this ST slide regarding timing:
The icing on the cake is the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In particular, the recently announced €360 million FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is a plum. While the European workforce will certainly be the first to benefit from this, it is a strong endorsement of FD-SOI and really good news for the entire FD-SOI ecosystem.
Chery sees big opportunities for FD-SOI. At the ST Technodays (4 June 2013), he told ASN he’s targeting mobile, as well as networking/servers, gaming and apps, including set-top boxes. (And he also hinted that we should be on the look-out for some big announcements.)
So those folks that give bulk FinFETs an edge in the race to 14nm better keep the pedal to the metal and their eyes on the road as FD-SOI has a tuned engine and a smooth track. Buckle your seatbelts: the race is on.
The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL.