At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor.
Here are some of the highlights (the complete presentations are all available from the CMP website).
Presented by Philippe Magarshack, Technology R&D Group Vice-President and Central CAD GM at STMicroelectronics – Download pdf
Presented by Jean-Marc Talbot, Senior Director of Engineering Analog & Mixed Signal at Mentor Graphics Grenoble R&D Center – Download pdf
The advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
A few other notables from the DATE conference:
CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.
What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafers. What you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.
The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.
The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2. At this point in scaling, that gets you about two million gates – about eight million transistors. So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.
Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.
Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.
The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.
CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.
The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.
CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.
In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:
Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.
For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.
These are real, leading edge chips and circuits we’re talking about. Here’s what you get:
The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:
The IO cells Libraries include:
You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.
So this represents a real opportunity. Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.
FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip. Wouldn’t you like to give it a try?
How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout.
The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio.
Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they can be coded in a straightforward manner using the Calibre user-friendly rule definition language and rule writer interface. Customers can simply augment their bulk CMOS rule decks by adding specific rules for SOI. Read More
Honeywell has worked with the top EDA tool vendors to develop the SOI process design kits (PDKs) needed by both in-house designers and foundry customers. Rick Veres, Honeywell EDA Manager, explains.
For digital rad-hard ASIC design, we worked with Synopsys to adapt the Pilot Design Environment to our process. The environment supports their entire RTL to GDSII flow, including all their synthesis tools, place and route, insertion and so forth—the standard industry flow. Our SOI cell libraries are all radhard optimized for commercial, military or satellite applications.
Honeywell provides mixed signal/analog SOI devices and cells to support a broad range of customer’s mixed mode ASICs. The design environment maintains all the digital capabilities while supplying analog cells and SRAM for true mixed signal ASICs. The design flow and associated Design Kits are supported for Cadence mixed signal tools.
For RFIC design and simulation, Honeywell’s SOI fab processes are supported by Cadence (Tality) PDKs, including RF Spectre.
For high temperature SOI CMOS, the Cadence PDK full-custom development library supports Cadence schematic capture, simulation, layout and verification tools.
Mentor Graphics has been very instrumental in helping us develop our SOI capability in their Calibre tool. We use Calibre to verify designs before we run them in the fab. There are some nuances that a user doesn’t see, that as a developer we do. For example, we have twice as many rules we have to implement and check in SOI versus standard bulk. But the complexity is all on the developer side. The user just runs it—it’s transparent to them. Mentor Graphics has done some significant and impressive work for us.